1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations

Abstract

We report, for the first time, on the 2-D boundary effects in a high performance 65nm SOI technology with dual Etch Stop Layer (dESL) stressors. 1-D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit design are also discussed. It will be shown that PMOS and ring oscillator performance can be significantly enhanced by optimizing the transverse and lateral placement of the dESL boundary.

Context dependent effects on LF (1/f) noise in advanced CMOS devices

“…3a, higher noise (3~5X) in A is observed in comparison with C that may be due to the presence of larger number of dummy poly in A. This conclusion is based on the hypothesis that lateral traps located at the poly-Si/STI interface are contributing to 1/f noise, which is in agreement with [2,4]. In addition, a second order effect -higher mechanical stress (compressive σ STI ) [5] may also impact 1/f.…”

“…The combination of feature size scaling and the use of novel materials to achieve performance enhancement in integrated circuits have resulted in CMOS devices display characteristics that are dependent on their proximity to adjacent devices [1,2]. Recent literature [1][2][3] discusses the impact on digital circuit performance but hitherto there has been little consideration of noise variations resulting from context layouts [4].…”

“…Recent literature [1][2][3] discusses the impact on digital circuit performance but hitherto there has been little consideration of noise variations resulting from context layouts [4]. Fig.…”

Compact model for layout dependent variability

“…For this variability-aware approach, it is necessary to examine which layout dependence should be incorporated and to build a compact model to describe them. Layout dependences such as LOD effect (1-4), DSL and contacts (5,6) or gate to gate space (7,8) and STI width effects (9-11) have been intensively studied and modeled. However, there are few literature reports of comprehensive model which is applicable in 45 nm CMOS at practical level (12).…”

CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design

“…The presence of adjacent NMOS and PMOS devices in the layout creates a DSL boundary. The location of the DSL boundary from the device has been shown to have geometry effects [7]. Proximity of DSL boundary may degrade or enhance device performance.…”