1.9-GHz wide-band if double conversion CMOS receiver for cordless telephone applications

Rudell, Jacques C.; Ou, Jia-Jiuinn; Cho, Thomas Byunghak; Chien, George; Brianti, F.; Weldon, Jeffrey A.; Gray, P.R.

doi:10.1016/s0920-5489(99)91945-1

Cited by 29 publications

(24 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Assuming a square-law MOSFET device, the conversion gain of Gilbert cell mixer can be approximated by averaging the gain over one period of LO signal [8].…”

Section: Circuit Performance Degradation Modelsmentioning

confidence: 99%

Soft breakdown and hot carrier reliability of CMOS RF mixer and redesign

Zhang³

et al.

2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280)

View full text Add to dashboard Cite

In this paper, CMOS RF down-conversion mixer circuit hot-carrier (HC) and soft breakdown (SBD) reliability estimation and redesign is presented. First of all, MOS transistor reliability under analog operation was evaluated by experiment. The mixer circuit operation conditions for the occurrence of HC and SBD are analyzed, and circuit performance model are presented to relate the device degradation to circuit performance degradation. Finally, we propose mixer circuit redesign strategies, which reduce the HC and SBD problem. Simulation shows improved noise performance with the similar gain, IIP3 and power consumption.I.

show abstract

“…Assuming a square-law MOSFET device, the conversion gain of Gilbert cell mixer can be approximated by averaging the gain over one period of LO signal [8].…”

Section: Circuit Performance Degradation Modelsmentioning

confidence: 99%

Soft breakdown and hot carrier reliability of CMOS RF mixer and redesign

Zhang³

et al.

2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280)

View full text Add to dashboard Cite

show abstract

“…1. The B part (the Hartley structure) can be implemented with analog mixer [7] or with digital functions [8]. The analog solution increase the size and the power consumption of the chip.…”

Section: B Mac Layermentioning

confidence: 99%

“…Unfortunately, image rejection increase the constraint on the analog functions performances. To achieve -35dBm image rejection the I1Q mismatch must be less than I degrees for phase and less than 150dBm for amplitude [7][8]. Moreover, digital Hartley structurc necd a best ADC's resolution than the conventional structure [9], resulting in a larger ADC's size.…”

Section: B Mac Layermentioning

confidence: 99%

Low cost solutions for 802.15.4 RF architectures

Bourdel

Pannier

Barthélémy

et al.

Eighth IEEE International Symposium on Spread Spectrum Techniques and Applications - Programme and Book of Abstracts (IEEE Cat.

View full text Add to dashboard Cite

This paper is a discussion about chip cost reduction by using an appropriate topology. This analysis is done in the context of the low-cost and low-rate 802.15 . 4 standard. Several architectures are discuss with CMOS analog, digital and mixed part considerations. The paper show the interest of solutions based on zero-IF topology and frequency shift keying (FSK) modulator comparatively to low-IF topology and quadrature phase shift keying (QPSK) modulation. Furthermore the 802.15 . . 4 standard is reviewed and the cost impact of the protocol IS highlighted. At least a complete (analog and digital) low-cost RF architecture is proposed for a full integration including all basic functions of the physical laycr.

show abstract

“…A typical differential LNA architecture is shown in [3]. With the emitter degeneration inductors and input matching network, the base impedance of the transistor can be transformed to another impedance required by the previous hand-selection filter to maximize the power transformation.…”

Section: B Lnamentioning

confidence: 99%

A SiGe WCDMA/DCS dual-band RF front-end receiver

Hsu

Chen

et al.

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003

View full text Add to dashboard Cite

Absfract -A WCDMAiDCS dual-band RF front-end receiver IC fabricated in a 0.35-pm SiGe BiCMOS technology is presented. This RF receiver uses P novel fullydifferential LNA with dual input-stages to replace the requirement of paralleling two similar LNAs in previous dual-band designs. This chip dissipates 24mA from a 2.7-V supply and can be used in direct-conversion or low-IF receiver. The measured voltage gain, PldB and iIP3 are 32dB, -25dBm and -1SdBm, respectively.

show abstract

1.9-GHz wide-band if double conversion CMOS receiver for cordless telephone applications

Cited by 29 publications

References 0 publications

Soft breakdown and hot carrier reliability of CMOS RF mixer and redesign

Soft breakdown and hot carrier reliability of CMOS RF mixer and redesign

Low cost solutions for 802.15.4 RF architectures

A SiGe WCDMA/DCS dual-band RF front-end receiver

Contact Info

Product

Resources

About