1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

Zerbe, J.; Chau, P.S.; Werner, C.; Thrush, T.; Liaw, Haw-Jyh; Garlepp, B.W.; Donnelly, Kevin

doi:10.1109/4.918912

Cited by 43 publications

(24 citation statements)

References 6 publications

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“…With a random sequence of 2 11 − 1, the BER was smaller than 10 −12 . Table I summarizes the performance of the proposed PWAM transceiver with several comparable PAM [2], [3] and PWM [9] over the past few years.…”

Section: Resultsmentioning

confidence: 99%

A PWM and PAM Signaling Hybrid Technology for Serial-Link Transceivers

Yang

2008

IEEE Trans. Instrum. Meas.

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Abstract-A 1-Gb/s 0.18-µm CMOS serial-link transceiver using multilevel pulse-width and pulse-amplitude modulation (PWAM) signaling and a pre-emphasis technique is presented. Based on the PWAM technique, the transmit signaling is implemented to effectively push high data rates through bandwidthlimited channels. The clock is implicitly embedded in the 4-bit data stream, and the associated overhead needed in the clock-and-data recovery circuitry can be mitigated. In addition, the pin count can be reduced by transferring the data channels and the clock channel over a single transmitted channel. The recovered clock has an rms jitter of 5.9 ps at 250 MHz, and the retimed data have an rms jitter of 13.7 ps at 250 Mb/s. The occupied die area is 1.65 × 1.40 mm 2 . The transmitter and receiver power consumption is 86 and 45 mW, respectively.Index Terms-Chip-to-chip communication, clock recovery, intersymbol interference (ISI), pulse-amplitude modulation (PAM), pulse-width modulation (PWM), serial link.

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Section: Resultsmentioning

confidence: 99%

A PWM and PAM Signaling Hybrid Technology for Serial-Link Transceivers

Yang

2008

IEEE Trans. Instrum. Meas.

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“…Instead of refining the sampling clock and precisely positioning its edge, widening the sampling widow can be viewed as a much easier option. To expand the timing window of BPM inductive links, we adopted the integrating receiver structure [8,9] shown in Fig. 2.…”

Section: Proposed Transceiver For Bpm Inductive Linksmentioning

confidence: 99%

“…Both a transmitter structure that can improve the quality of the transmitted signal and a receiver circuit that dramatically widens the data sampling time window are then proposed. Especially, we first recognize the effectiveness of the integrating receiver [8,9] in the BPM inductive link and successfully demonstrate its superior performance. Circuit details are discussed along with the simulation results in Section III, while the measurement results are given in Section IV.…”

Section: Introductionmentioning

confidence: 99%

An Inductive-coupling Link with a Complementary Switching Transmitter and an Integrating Receiver

Jeong¹,

Kim²,

Kim³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A transceiver for a high-speed inductivecoupling link is proposed. The bi-phase modulation (BPM) signaling scheme is used due to its good noise immunity. The transmitter utilizes a complementary switching method to remove glitches in transmitted data. To increase the timing margin on the receiver side, an integrating receiver with a pre-charging equalizer is employed. The proposed transceiver was implemented via a 130-nm CMOS process. The measured timing window for a 10 -12 bit error rate (BER) at 1.8 Gb/s was 0.33 UI.

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“…Once the signals are corrupted, catastrophic system failures may occur. To increase electronic systems potential, advanced package technology such as flip-chip ball grid array (BGA), multichip-module (MCM) configurations are often used to reduce package parasitics and there also has been a great deal of interest in the use of multiple level signaling [3,7], equalization techniques [5,6] to overcome bandwidth limitations of interconnections. Robust system should also independent of process, voltage, and temperature (PVT) variation.…”

Section: Introductionmentioning

confidence: 99%