1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme

Kanda, Kensuke; Antono, Danardono Dwi; Ishida, Koichi; Kawaguchi, Hiroshi; Kuroda, Tadahiro; Sakurai, Takayasu

doi:10.1109/isscc.2003.1234260

Cited by 118 publications

(66 citation statements)

References 1 publication

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“…• Capacitive coupling [9] connects the known-good-dies without wire connections. However, only the face-to-face connection is allowed; so the number of stacked dies is limited to only two.…”

Section: Wireless 3-d Interconnectionmentioning

confidence: 99%

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A vertical bubble flow network using inductive-coupling for 3-D CMPs

Matsutani

Take

Sasaki

et al. 2011

Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

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A wireless 3-D NoC architecture for CMPs, in which the number of processor and cache chips stacked in a package can be changed after the chip fabrication, is proposed by using the inductive coupling technology that can connect more than two known-good-dies without wire connections. Each chip has data transceivers for uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a single vertical ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring network, we use the bubble flow control which is more flexible and efficient compared to the conventional VC-based deadlock avoidance. We implemented a real 3-D chip that has onchip routers and inductive-coupling data transceivers using a 65nm process in order to show the feasibility of our proposal. The vertical bubble flow control is compared with the conventional VC-based approach and vertical bus in terms of the throughput, hardware amount, and application performance using a full system CMP simulator. The results show that the proposed vertical bubble flow network outperforms the VC-based approach by 7.9%-12.5% with a 33.5% smaller router area. *

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Section: Wireless 3-d Interconnectionmentioning

confidence: 99%

“…Various interconnection technologies have been developed to be used as a medium for the 3-D NoCs: wire-bonding, micro-bump [4,12], wireless (e.g., capacitive or inductive coupling) [7,9,19,20] between stacked dies, and throughsilicon via (TSV) [5,7] between stacked wafers. The comparisons of these 3-D IC technologies are discussed in [7].…”

Section: Introductionmentioning

confidence: 99%

A vertical bubble flow network using inductive-coupling for 3-D CMPs

Matsutani

Take

Sasaki

et al. 2011

Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

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“…Wireless interconnections are classified into capacitive coupling [4] and inductive coupling [5,6,7]. Since the use of capacitive coupling is limited to face-to-face stacking of two chips, inductive coupling which can interconnect more than two chips has been mainstream of wireless chip stacking.…”

Section: Introductionmentioning

confidence: 99%

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Nomura

Matsushita

Kadomoto

et al. 2018

IJNC

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A wireless inductive coupling ThruChip Interface (TCI) is a flexible system-in-package (SiP) technique which enables to build a powerful interconnection network between stacked chips. For easy use of TCI, we have developed intellectual properties (IPs), and proposed an interconnection network which can make the use of IPs. We also developed a real chip embedded the IP, and evaluated the performance. By stacking multiple chips with the proposed IP, an inter-chip network with link-to-link flow control by piggyback control is established. The new proposed escalator network which uses piggyback of the credit packets outperforms the ring network used in the first prototype by 28%-59% in terms of throughput. The performance overhead by the piggyback control was less than 3%-4% of that without control messages.

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“…To address this particular challenge, both clocked [3] and clock-less [4], [5], [6] approaches have been investigated. The clock-less receiver architectures implemented in [4], [5], [6] recover the NRZ data using a non-linear circuit to restore the lost low fequency signal content; the clock is then recovered using traditional clock recovery techniques from the NRZ signal.…”

Section: Introductionmentioning

confidence: 99%

A 14-Gb/s 32 mW AC coupled receiver in 90-nm CMOS

Hossain

Carusone

2007

2007 IEEE Symposium on VLSI Circuits

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This paper introduces a high-speed AC coupled receiver architecture for high density interconnects. The proposed architecture combines a novel hysteresis circuit path and a linear broadband amplifier path to recover a NRZ signal from an 80-fF capacitively coupled channel. Using this dual path technique, a 90-nm CMOS prototype achieves 14-Gb/s operation while consuming 32 mW from a 1.2-V supply. The measured sensitivity of the receiver is better than 100 mVp-p differential.

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1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme

Cited by 118 publications

References 1 publication

A vertical bubble flow network using inductive-coupling for 3-D CMPs

A vertical bubble flow network using inductive-coupling for 3-D CMPs

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

A 14-Gb/s 32 mW AC coupled receiver in 90-nm CMOS

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