1.0 &amp;amp;#181;m CMOS process for highly stable tera-ohm polysilicon load 1Mb SRAM

Hoshi, Nagahiro; Kayama, Shinji; Nishihara, T.; Aoyama, J.; Komatsu, Takahiro; Shimada, Takuya

doi:10.1109/iedm.1986.191175

Cited by 13 publications

(12 citation statements)

References 1 publication

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“…Hence, the polysilicon thickness was fixed at 550A, similarly to a value already reported (15). It was d e e m e d inappropriate to vary the polysilicon thickness after noticing that this parameter had secondary influence on the bird's beak size and that it could be more advantageously optimized according to process manufacturability considerations.…”

Section: Resultsmentioning

confidence: 99%

LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

Ghezzo

Kaminsky

Nissan-Cohen

et al. 1989

J. Electrochem. Soc.

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Local oxidation of polysilicon over silicon (tOPOS) isolation has been characterized for use in a 0.8 ~m CMOS/BULK process with reduced field oxide edge encroachment (bird's beak). Compared to the standard local oxidation of silicon (LOCOS) LOPOS adds a thin polysilicon layer between the stress relief oxide and the overlying nitride without changing the active area patterning procedure. To optimize the LOPOS structure, the thickness of the oxide and nitride layers was varied in a fully-factorial experiment, measuring the bird's beak and checking for the presence of silicon edge defects. It was found }hat for a 6000A field oxide the bird's beak can be safely reduced to =0.3 I~m per side with tOPOS, which is significantly less than =0.55 ~m with LOCOS. The corresponding stack consisted of 1500,~ Si3N4/550A polysilicon (undoped)/ 200A SiO2. LOPOS fabricated diodes exhibited low leakage of <0.5 nA/cm 2 and <0.5 pA/cm for the area and edge components, respectively, while MOS capacitors were breakdown-free up to 8 MV/cm during voltage-stress tests, compared to 6 MV/cm for LOCOS. ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 157.182.150.22 Downloaded on 2015-04-12 to IP

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Section: Resultsmentioning

confidence: 99%

LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

Ghezzo

Kaminsky

Nissan-Cohen

et al. 1989

J. Electrochem. Soc.

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“…6) A semiinsulation film employing n-p compensation doping has a lower temperature coefficient and promises a higher resistivity. Hoshi et al, 7) showed that hydrogen plasma could effectively improve a performance of the polysilicon film, in particular, control the resistivity. This is attributed to the fact that hydrogen atoms can effectively passivate the dangling bonds in the grain boundaries of polysilicon thin films 8) and neutralize dopants; as a result, the resistivity of polysilicon films is increased.…”

Section: Introductionmentioning

confidence: 99%

Hydrogen and Oxygen Plasma Effects on Undoped and n–p Compensation-doped Single- and Multilayer Polycrystalline Silicon Resistor Films

Liou

Chang

Wang

2005

Jpn. J. Appl. Phys.

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In this study, we investigate hydrogen and oxygen plasma effects on undoped and n-p compensation-doped polycrystalline silicon (poly-Si) resistors. The current-voltage (I-V) characteristics, channel resistance (R p ), contact region resistance (R j ), total resistance (R T ¼ R p þ R j ), and activation energy of the poly-Si resistors with different film lengths and passivation layers were measured and analyzed. It is found that the film resistance has been strongly enhanced by either hydrogen or oxygen plasma treatments, which is attributed to the neutralization effect of plasma treatment inside the grain being overridden by the passivation effect at the grain boundary. Moreover, it is seen that both the total resistance and activation energy of undoped intrinsic films are larger than those of n-p compensation-doped films. To realize a high-value poly-Si resistor, a novel multilayer structure is proposed for the first time. Compared with the conventional single-layer structure, it is seen that the relatively smaller grain size in a four-layer structure results in an approximately 25-50% increase in resistance.

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“…All involved complicated processing sequences. Poly-buffer LOCOS (PBL), using a stress relief layer of polysilicon between the oxide and silicon nitride films, has been proposed to reduce the lateral encroachment of field oxide into the active areas to a value of 0.1-0.2 pm per side in comparison to the 0.5 pm per side of conventional LOCOS [5] for 0.8-pm CMOS technology, and has been demonstrated yield in 1-Mb SRAM [6]. In this letter, a new LOCOS process, utilizing the principle of a stress relief polysilicon layer and a reverse L-shape sealed nitride spacer design, is proposed to further reduce bird's beak to less than 0.05 pm without introducing defects.…”

Section: Introduction He Conventional Locos (Local Oxidation Of Silicon)mentioning

confidence: 99%

Reverse L-shape sealed poly-buffer LOCOS technology

Sung

Lu²,

Fritzinger³

et al. 1990

IEEE Electron Device Lett.

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This paper describes a new LOCOS (local oxidation of silicon) isolation process, reverse L-shape sealed poly-buffer LOCOS (RLS-PBL), which can effectively eliminate the bird's beak without introducing defects. In this process, the pad oxide film is selectively etched using the silicon nitride/polysilicon stack as a mask to form undercut portions. Thermal oxidation is then performed to grow a new thin oxide film to cover the entire silicon surface including the undercut portions to provide a new stress-buffer oxide film prior to a thin silicon nitride deposition. The reverse L-shape sealed silicon nitride spacer is formed by RIE etching. Reverse leakage currents of NMOS submicrometer MOSFET devices, edge diodes, and capacitors fabricated by the new isolation process are comparable to those of the conventional LOCOS and poly-buffer LOCOS, and are much superior to the sealedinterface LOCOS'S. The defect-free mechanism and nearly zero bird's beak characteristics are attributed to the stress-absorption polycrystalline Mm in conjunction with the special reverse L-shape silicon nitride spacer design.

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1.0 &#181;m CMOS process for highly stable tera-ohm polysilicon load 1Mb SRAM

Cited by 13 publications

References 1 publication

LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

Hydrogen and Oxygen Plasma Effects on Undoped and n–p Compensation-doped Single- and Multilayer Polycrystalline Silicon Resistor Films

Reverse L-shape sealed poly-buffer LOCOS technology

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