0.5¿ CMOS 2.4 GHz RF-Switch for Wireless Communications

Mekanand, Piya; Prawatrungruang, P.; Eungdamrong, Duangrat

doi:10.1109/icact.2008.4493799

Cited by 6 publications

(7 citation statements)

References 7 publications

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“…These resistances are used to mitigate the voltage fluctuations around the gate terminal which can affect the channel resistance as well as can cause breakdown at the gate terminal [15]. Moreover, in order to keep the switching speed of the transistor, choosing a suitable gate bias resistor is very important [16]. So, we used 5 KΩ resistors for body floating (R B1 -R B6 ) and 5 Ω for gate biasing (R G1 -R G6 ).…”

Section: Design Of a Nanoswitch In 130 Nm Cmos Technology For 24 Ghzmentioning

confidence: 99%

Design of a nanoswitch in 130 nm CMOS technology for 2.4 GHz wireless terminals

Bhuiyan¹,

Reaz²,

Jalil³

et al. 2014

Bulletin of the Polish Academy of Sciences Technical Sciences

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Abstract. This paper proposes a transmit/receive (T/R) nanoswitch in 130 nm CMOS technology for 2.4 GHz ISM band transceivers. It exhibits 1.03-dB insertion loss, 27.57-dB isolation and a power handling capacity (P1 dB) of 36.2-dBm. It dissipates only 6.87 µW power for 1.8/0 V control voltages and is capable of switching in 416.61 ps. Besides insertion loss and isolation of the nanoswitch is found to vary by 0.1 dB and 0.9 dB, respectively for a temperature change of 125• C. Only the transistor W/L optimization and resistive body floating technique is used for such lucrative performances. Besides absence of bulky inductors and capacitors in the schematic circuit help to attain the smallest chip area of 0.0071 mm 2 which is the lowest ever reported in this frequency band. Therefore, simplicity and low chip area of the circuit trim down the cost of fabrication without compromising the performance issue.

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Section: Design Of a Nanoswitch In 130 Nm Cmos Technology For 24 Ghzmentioning

confidence: 99%

Design of a nanoswitch in 130 nm CMOS technology for 2.4 GHz wireless terminals

Bhuiyan¹,

Reaz²,

Jalil³

et al. 2014

Bulletin of the Polish Academy of Sciences Technical Sciences

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show abstract

“…Nevertheless, they reduced the size of the chip [13]. Mekanand et al (2008) designed a switch by paralleling an NMOS and a PMOS instead of a single MOS to improve the dynamic range in the conducting state, but the IL of the switch was more than 1 dB [14]. Dinc et al (2012) used inductors in parallel to switching transistors in order to form a parallel tank circuit and cancel out some of the transistors' off-state drainsource capacitance [15].…”

Section: Introductionmentioning

confidence: 99%

A fully integrated high IP1dB CMOS SPDT switch using stacked transistors for 2.4 GHz TDD transceiver applications

et al. 2018

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A transmit/receive (T/R) switch is an essential module of every modern time division duplex (TDD) transceiver circuit. A T/R switch with high power handling capacity in CMOS process is difficult to design due to capacitive coupling of radio frequency signals to the substrate. This paper proposes a single-pole-doublethrow (SPDT) T/R switch designed in a standard Silterra 130 nm CMOS process for high-power applications like RFID readers. The results reveal that, in 2.4 GHz ISM band, the proposed switch exhibits a very high input P1dB of 39 dBm with insertion loss of only 0.34 dB and isolation of 40 dB in transmit mode but 1.08 dB insertion loss and 30 dB isolation in receive mode. Stacked thick-oxide triple-well transistors, resistive body floating and negative control voltages are used to achieve such lucrative performance. Moreover, the chip size of the designed switch is only 0.034 mm 2 as bulky inductors and capacitors are avoided. The Monte-Carlo and corner analyses confirm that the performance of the switch is also quite stable and reliable.

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“…Manku [2] has discussed the design issues and the microwave properties of CMOS devices with qualitative understanding of the microwave characteristics of the MOS transistors which is helpful for IC circuit design to create better front-end radio-frequency CMOS circuits and presented the network properties of CMOS devices, the frequency response, the microwave noise properties and scaling rule. Mekanand et al [3] have proposed a transceiver CMOS switch for 2.4 GHz with low insertion loss and excellent control voltage. These simulation results of CMOS switch design demonstrate an insertion loss of 1.102 dB for receiving mode and 1.085 dB for transmitting mode.…”

Section: Introductionmentioning

confidence: 99%

Capacitive Model and S-Parameters of Double-Pole Four-Throw Double-Gate RF CMOS Switch

Srivastava¹,

Yadav²,

Singh³

2011

WET

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In this paper, we have analyzed the Double-Pole Four-Throw Double-Gate Radio-Frequency Complementary Metal-Oxide-Semiconductor (DP4T DG RF CMOS) switch using S-parameters for 1 GHz to 60 GHz of frequency range. DP4T DG RF CMOS switch for operation at high frequency is also analyzed with its capacitive model. The re-sults for the development of this proposed switch include the basics of the circuit elements in terms of capacitance, re-sistance, impedance, admittance, series equivalent and parallel equivalent of this network at different frequencies which are present in this switch whatever they are ON or OFF

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0.5¿ CMOS 2.4 GHz RF-Switch for Wireless Communications

Cited by 6 publications

References 7 publications

Design of a nanoswitch in 130 nm CMOS technology for 2.4 GHz wireless terminals

Design of a nanoswitch in 130 nm CMOS technology for 2.4 GHz wireless terminals

A fully integrated high IP1dB CMOS SPDT switch using stacked transistors for 2.4 GHz TDD transceiver applications

Capacitive Model and S-Parameters of Double-Pole Four-Throw Double-Gate RF CMOS Switch

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