Non-binary low-density parity-check codes are robust to various channel impairments. However, based on the existing decoding algorithms, the decoder implementations are expensive because of their excessive computational complexity and memory usage. Based on the combinatorial optimization, we present an approximation method for the check node processing. The simulation results demonstrate that our scheme has small performance loss over the additive white Gaussian noise channel and independent Rayleigh fading channel. Furthermore, the proposed reduced-complexity realization provides significant savings on hardware, so it yields a good performance-complexity tradeoff and can be efficiently implemented. Index TermsLow-density parity-check (LDPC) codes, non-binary codes, iterative decoding, extended min-sum algorithm.

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The presence of error floor in low density parity check (LDPC) codes is of great concern for potential applications of LDPC codes to data storage channels, which require the error correcting code (ECC) to maintain the near-capacity error correcting performance at frame error rate as low as 10 −12 . In order to investigate the error floor of LDPC codes under partial response channels used in data storage systems, we propose a new estimation method combining analytical tools and simulation, based on the concept of trapping sets. The definition of trapping sets is based on the dominant error patterns observed in the decoding process. The goal is to accurately estimate the error rate in the error floor region for certain types of LDPC codes under the partial response channel and further extend the frame error rate down to 10 −14 or lower. Towards this goal, we first use field programmable gate array (FPGA) hardware simulation to find the trapping sets that cause the decoding failure in the error floor region. For each trapping set, we extract the parameters which are key to the decoding failure rate caused by this trapping set. Then we use a much simpler in situ hardware simulation with these parameters to obtain the conditional decoding failure rate. By considering all the trapping sets we find, we obtain the overall frame error rate in the error floor region. The estimation results for a length-4623 QC-LDPC code under the EPR4 channel are within 0.3 dB of the direct simulation results. In addition, this method allows us to estimate the frame error rate of a LDPC code down to 10 −14 or lower.

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This paper presents methods for efficient encoding of quasi-cyclic LDPC codes. Based on these methods, encoding of quasi-cyclic LDPC codes can be implemented using simple shiftregisters with complexity linearly proportional to the number of parity-check bits of a code for serial encoding and to the length of a code for parallel encoding. Various encoding circuits are devised and they provide a range of trade-offs between encoding complexity and speed. IEEE Globecom 2005 1205 0-7803-9415-1/05/$20.00 © 2005 IEEE 0-7803-9415-1/05/$20.00 © 2005 IEEE 0-7803-9415-

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