A negative capacitance transistor (NCFET) with fully depleted silicon-on-insulator (FDSOI) technology (NC-FDSOI) is one of the promising candidates for next-generation low-power devices. However, it suffers from the inherent negative differential resistance (NDR) effect, which is very detrimental to device and circuit designs. Aiming at overcoming this shortcoming, this paper proposes for the first time to use local Gaussian heavy doping technology (LoGHeD) in the channel near the drain side to suppress the NDR effect in the NC-FDSOI. The technical computer-aided design (TCAD) simulation results have validated that the output conductance (GDS) with LoGHeD, which is used to measure the NDR effect, increases compared to the conventional NC-FDSOI counterpart and approaches zero. With the increase in doping concentration, the inhibitory capability of the NDR effect shows a monotonously increasing trend. In addition, the proposed approach maintains and even enhances performances of the NC-FDSOI transistor regarding the electrical parameters, such as threshold voltage (VTH), sub-threshold swing (SS), switching current ratio (ION/IOFF), and drain-induced barrier lowering (DIBL).
The effect of three double-layer spacers (corner/selective/dual) on the performance of a negative-capacitance nanosheet field-effect transistor (NC-NSFET) was investigated for the first time. Sentaurus technology computer-aided design simulations revealed that the NC-NSFET with corner
spacer will be significantly improved in transfer and high frequency characteristics due to the increase of ferroelectric layer thickness, and the NC-NSFET with a selective spacer structure exhibits better gate controllability. Compared with the ordinary dual-k spacer structure, the
switching current ratio is doubled, and its subthreshold swing and drain-induced barrier lowering are reduced by 3.0% and 48%, respectively. In addition, by introducing a selective spacer at the source side and a corner spacer at the drain side, the NC-NSFET has a smaller intrinsic delay and
exhibits better capacitance matching and stronger gate controllability than that with a symmetric spacer. For the double-layer spacer, the extension of the high-k spacer in the horizontal direction is more beneficial to the improvement of the device performance than that in the vertical
direction, which provides a more comprehensive reference for the spacer application in NC-NSFET.
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