Abstract:In this express, we have proposed an improved architecture for designing efficient modulo (2 n − 2 p + 1) multipliers on the condition n ≥ 2p. The proposed modulo (2 n − 2 p + 1) multipliers can improve the current state of the art by 7.7-42.5% in terms of area and 13.1-44.2% in terms of performance delay on the average or by 60.5% in terms of area with the equivalent delay performance.
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