Binary decision diagrams (BDDs) are effective means to cope with complex concurrent system. But the size of BDD itself can be relatively large. We study the BDD representation of large synchronous, asynchronous and interleaved processes with communication via shared variables. Due to the features of communication, we introduce a novel representation strategy. Based on the model, we continue to model and map up the synchrony, and detect the deadlock errors.
Abstract.With the continuous increase in the size and complexity of a real-time computer system, the use of formal verification methods in software development is also on the rise. The traditional formal verification method is not fully applicable to the development of actual system life cycle. Therefore, this paper presents a new real-time system verification method, It take the deadlock timed B u chi ⋅⋅ automata as the medium, and translate the timed temporal logic into timed communicating sequential process language. The tock event is also joined, which can be directly used for the detection of refinement tool FDR. The method verifies the situation of deadlock. To establish the link between the conventional model checking and refinement model checking can well combine the advantages of both and improve system security and reliability.
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