In this article, a lumped-element balun with multi-interference suppression is implemented and presented. Originated from the conventional lattice LC balun, the balun combining two Π-networks is expended to four new topologies. By constructing frequency traps and out-of-phase combining pathways, the new topologies can realize two-or three-interference suppression while maintaining well-matched input/output impedances. The concept is studied theoretically in both even and odd mode circuits, and analytical design equations are also derived. Based on the design theory, four interference suppression balun topologies are proposed for push-pull power amplifiers. To verify the design concept, two of the four topologies working at 1 GHz are prototyped and measured. The measured results agree well with the analysis and simulation results. The two baluns both achieve good performance with low insertion loss better than À3.9 dB, low return loss less than À13.6 dB, good interference suppression more than 24.7 dB, and small phase unbalance less than 0.8 . Furthermore, the proposed balun is used in a gallium nitride push-pull power amplifier to validate the 2nd and 3rd harmonic suppression. The amplifier works at 1 GHz with a typical gain of 16.7 dB. At least À45 dBc interference suppression, 52.6% power-added efficiency, and 34.6 dBm P1dB output power are obtained.

A novel high precision and high PSRR bandgap voltage reference with improved high-order temperature compensation is proposed in this paper. An accurate curvature compensation topology is designed to compensate the reference voltage in the high and low temperature sections respectively. A pre-regular circuit is deployed to improve the PSRR and enlarge input voltage range. Implemented with TSMC 0.18um process, this design achieves an ultra-low temperature coefficient (TC) of 1.166ppm/°C from −40 °C to 125 °C with a high PSRR of -80dB at 1KHz.

This paper presents a low‐power self‐contained overvoltage detector. Compared with conventional detectors that consist of stacked Zener diodes, the proposed structure can trim the threshold with binary codes to accommodate system‐level changes. The proposed structure enables trimming by adding a decoder, a biasing circuit, and switches in parallel with Zener diodes. The newly configured structure forms a standalone detector that can operate independently and be powered from the supply under detection with negligible current addition. The proposed structure is applicable to any high‐voltage process that contains N‐type isolation layer and needs no high‐voltage device. The proposed circuit with three bits adjustment circuit was fabricated in a 0.18 μm Bipolar‐CMOS‐DMOS (BCD) process, the overvoltage threshold can be adjusted from 8 to 38 V with post trim variation of ±2.5 V. The measured quiescent current was around 0 μA at 10 V and 28 μA at 38 V, which was comparable to the current consumption in a conventional structure with 38 V overvoltage threshold. © 2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

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