This Letter presents a low-voltage comparator, which incorporates bulk-driven structure to enhance the comparison speed. The bulk nodes of the cross-coupled transistors are biased with proper voltages in the sampling phase to lower their threshold voltages, and the input signal is then coupled to the bulk nodes in the comparison phase to provide extra transconductance. With the proposed structure, the comparator designed in 65-nm CMOS achieves a comparison delay of 120 ps for 0.1-mV input amplitude, which is suitable for 7-GSPS ADCs with resolution over 12 bit at 1.2-V Vpp input. The comparison speed is improved by >20% compared to a conventional comparator without the bulk-driven structure.
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