Triple modular redundancy (TMR) is widely used in FPGA/ASIC circuits to protect circuits against single event upsets (SEUs). However, because of the interference of metastability on signal transmission across clock domains, the TMR circuits' capability against SEUs is reduced greatly. In order to solve this problem, a cross-clock transmission solution which could be applied in TMR circuits are presented. In addition, simulationbased verification which combined protocol assertions, metastable injection and forced inversion is proposed to succeed in verifying the availability of the solution based on TMR circuits.
There are a large number of multi-clock domain circuits in the airborne equipment of aircraft. When data is transmitted across the clock domain, meta-stability may occur, resulting in data transmission errors and reduced circuit reliability. However, due to the occasional and non-reproducible faults caused by metastability, and the high cost of existing cross-clock domain specific verification software, cross-clock domain circuit verification in three-mode redundancy scenarios is not supported. To solve this problem, a method that combines register transfer level (RTL) validation, board-level accelerated testing and computational evaluation based on traditional tools is presented. This method can detect the cross-clock domain transmission problems in three-mode application scenarios or normal scenarios and assess potential cross-clock domain transmission risks using generic simulation tools at an early stage of design. It reduces the cost of economy and time for high safety level airborne complex electronic verification, and improves the reliability of the circuit.
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