This work for the first time reports engineered oxygen-deficient, blue TiO2 nanocrystals with coexposed {101}-{001} facets (TiO2–x {001}-{101}) to enhance CO2 photoreduction under visible light. The TiO2–x {001}-{101} material demonstrated a relatively high quantum yield (0.31% under UV–vis light and 0.134% under visible light) for CO2 reduction to CO by water vapor and more than 4 times higher visible light activity in comparison with TiO2 with a single {001} plane or {101} plane and TiO2(P25). Possible reasons are the exposure of more active sites (e.g., undercoordinated Ti atoms and oxygen vacancies), the facilitated electron transfer between {001} and {101} planes, and the formation of a new energy state (Ti3+) within the TiO2 band gap to extend the visible light response. An in situ diffuse reflectance infrared Fourier transform spectroscopy (DRIFTS) study was applied to understand the roles of coexposed {001}-{101} facets and Ti3+ sites in activating surface intermediates. The in situ DRIFTS analysis suggested that the coexposed {001}-{101} facets increased the capacity of reversible CO2 adsorption and that the combination of {001}-{101} and Ti3+ enhanced the activation and conversion kinetics of adsorbed species. The visible light responsive TiO2–x {001}-{101} material is not oxidized after long-term exposure to an air environment. This work is a significant contribution to the design of efficient and stable solar fuel catalysts.

Physical unclonable functions (PUFs) are a strong and secure root source for identification and authentication applications. PUFs are especially valuable in FPGA-based systems because FPGA designs are vulnerable to intellectual property (IP) thefts and cloning, which PUFs protect against by generating random but device-specific bitstrings. Theoretically, the randomness of PUFs originates from variations in the manufacturing process. PUFs should be free of deterministic variation owing to the systematic bias among all chips of the same model. Correspondingly, one of the major challenges for FPGA-based PUFs is the difficulty of avoiding systematic bias between nominally matched delays in competing paths. In this paper, a deep investigation into the LUT structure on a Xilinx FPGA was conducted. Based on the investigation findings, a compact PUF design based on programmable look-up table paths is proposed. The proposed intertwined structure and the novel 2-phase, 2-pass scheme significantly reduced the impact of systematic biases in the Xilinx FPGA LUT. The proposed PUFs exploit random variations in LUTs, thus exhibiting very good uniformity and uniqueness among the generated bitstrings.

Physically unclonable functions (PUFs) are hardware security primitives that utilize nonreproducible manufacturing variations to provide device-specific challenge-response pairs (CRPs). Such primitives are desirable for applications such as communication and intellectual property protection. PUFs have been gaining considerable interest from both the academic and industrial communities because of their simplicity and stability. However, many recent studies have exposed PUFs to machine-learning (ML) modeling attacks. To improve the resilience of a system to general ML attacks instead of a specific ML technique, a common solution is to improve the complexity of the system. Structures, such as XOR-PUFs, can significantly increase the nonlinearity of PUFs to provide resilience against ML attacks. However, an increase in complexity often results in an increase in area and/or a decrease in reliability. This study proposes a lightweight ring oscillator (RO)-based PUFs using an additional modulus process to improve ML resiliency. The idea was to increase the complexity of the RO-PUF without significant hardware overhead by applying a modulus process to the outcomes from the RO frequency counter. We also present a thorough investigation of the design space to balance ML resiliency and other performance metrics such as reliability, uniqueness, and uniformity.

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Compact FPGA based PUF extraction circuits based on intertwined programmable delay paths implemented on Xilinx FPGA.