Titanium nitride (TiN) not only was utilized in the wear-resistant coatings industry but it was also adopted in barrier processes for semiconductor manufacturing. Barrier processes include the titanium (Ti) and TiN processes, which are commonly used as diffusion barriers in via/contact applications. However, engineers frequently struggle at the via/contact module in the beginning of every technology node. As devices shrink, barrier processes become more challenging to overcome the both the physical fill-in and electrical performance requirements of advanced small via/contact plugs. The aim of this paper is to investigate various chemical vapor deposition (CVD) TiCl 4 -based barrier processes to serve the application of advanced small via/contact plugs and the metal gate processes. The results demonstrate that the plasma-enhanced chemical vapor deposition (PECVD) TiCl 4 -based Ti process needs to select a feasible process temperature to avoid Si surface corrosion by high-temperature chloride flow. Conventional high step coverage (HSC) CVD TiCl 4 -based TiN processes give much better impurity performance than metal organic chemical vapor deposition (MOCVD) TiN. However, the higher chloride content in HSC film may degrade the long-term reliability of the device. Furthermore, it is evidenced that a sequential flow deposition (SFD) CVD TiCl 4 -based process with multiple cycles can give much less chloride content, resulting in faster erase speeds and lower erase levels than that of conventional HSC TiN.
The behavior of barrier engineered charge trapping devices incorporating Al 2 O 3 and HfO 2 high-K layers has been critically examined. We propose to use a thicker buffer oxide (> 6 nm) and thin (<5nm) high-K top capping layer for BE-MAONOS and BE-MHONOS in order to improve the reliability. Thinner high-K top capping layer reduces the fast initial charge loss under high-temperature baking. Moreover, it also reduces the undesired transient read current relaxation. These effects are due to the bulk trapped charge in high-K material during programming/erasing. By reducing the high-K thickness these reliability issues can be minimized. We also found that HfO 2 has a better thickness scaling capability than Al 2 O 3 . Finally, a high-performance BE-SHONOS (with n + -poly gate and HfO 2 top capping layer) transistor is demonstrated in this work.
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