This paper proposes a novel VLSI architecture of GNSS acquisition engine based on shorttime correlation combined with an FFT scheme. The architecture supports multi-constellation systems and multi-frequency satellite signals flexibly by the manner of time-division multiplexing. The supported signals include GPS, BDS, GLONASS, GALILEO, QZSS, IRNSS, and SBAS. Compared with other direct acquisition structures, the search efficiency of the acquisition engine is improved by using the IF playback structure. Based on the characteristics of L1C and B1C signal spread spectrum codes, an efficient generation method and the circuit structure of Legendre sequence which is compatible with L1C and B1C spread spectrum codes are proposed. It can effectively reduce the die area of the spread spectrum code generator and the generation time of the L1C/B1C spread spectrum code. Combining with the acquisition scheme adopted in this paper, the structure of the short-time correlators' array is optimized, and the maximum clock frequency of the acquisition engine is significantly improved. The acquisition engine proposed in this paper is implemented in a 55-nm CMOS technology. The system occupied a silicon area of 2.1 mm 2 and consumes only 72.02-mW power while realizing the maximum clock frequency at about 333.33 MHz.

It is well known that there are micro-architectural vulnerabilities that enable an attacker to use caches to exfiltrate secrets from a victim. These vulnerabilities exploit the fact that the attacker can detect cache lines that were accessed by the victim. Therefore, architects have looked at different forms of randomization to thwart the attacker's ability to communicate using the cache. The security analysis of those randomly mapped caches is based upon the increased difficulty for the attacker to determine the addresses that touch the same cache line that the victim has accessed.In this paper, we show that the analyses used to evaluate those schemes were incomplete in various ways. For example, they were incomplete because they only focused on one of the steps used in the exfiltration of secrets. Specifically, the step that the attacker uses to determine the set of addresses that can monitor the cache lines used by the transmitter address. Instead, we broaden the analysis of micro-architecture side channels by providing an overall view of the communication process. This allows us to identify the existence of other communication steps that can also affect the security of randomly mapped caches, but have been ignored by prior work.We design an analysis framework, CaSA, to comprehensively and quantitatively analyze the security of these randomly mapped caches. We comprehensively consider the end-to-end communication steps and study the statistical relationship between different steps. In addition, to perform quantitative analysis, we leverage the concepts from the field of telecommunications to formulate the security analysis into a statistical problem. We use CaSA to evaluate a wide range of attack strategies and cache configurations. Our result shows that the randomization mechanisms used in the state-of-the-art randomly mapped caches are insecure.Index Terms-Micro-architecture side channel, randomly mapped cache, security analysis.

In this paper we propose an architecture of the anti-jamming circuit in high precision GNSS receiver chip base on the frequency-time domain solution, at most, the jamming signals of 12 frequency points can be detected and eliminated at the same time. In addition, an jamming detection strategy based on short-long time FFT is proposed and a circuit of FFT engine with low cost is designed to reduce the area and dynamic power of the GNSS receiver chip. Finally, we complete the VLSI design by using 55 nm digital process, the circuit area is 0.082 mm 2 , the average dynamic power is 0.943 mW. The implementation results prove the effectiveness of the proposed anti-jamming circuit.

In this paper, a novel architecture of area-effective high-radix floating-point divider with low power consumption is proposed. By extending the principle of the standard SRT algorithm, the divider can estimate the partial quotient digits by a simpler circuit and tolerate certain calculation errors in each recurrence cycle. In addition, the accumulation of errors in the recurrence process can be eliminated automatically without additional calculation cycle. The latency and area cost of the divider are linear with the radix number, which solves the problem that the quotient digits selection tables in high-radix divider have high area cost. Base on the proposed architecture a single-precision floating-point divider is implemented, which has an area of 6037.20um 2 in 65nm process. The dynamic power consumption of the divider is only 0.848mW at 250MHz. Compared with other dividers reported in the literature, the area cost can be reduced by about 90% with the same computation precision and performance.INDEX TERMS High-radix, division, SRT, quotient-digits-selection.