As the timing delay becomes a critical issue of the chip performance, there comes a burning desire for IC design under smart manufacturing to optimize the delay. As the best connection model for multi-terminal nets, the wirelength and the maximum source-to-sink pathlength of the Steiner minimum tree are both the decisive factors of timing delay for routing. In addition, considering that X-routing can get the utmost out of routing resources, this paper proposes a Timing-Driven X-routing Steiner Minimum Tree (TD-XSMT) algorithm based on two-stage competitive particle swarm optimization. The paper utilizes the multi-objective particle swarm optimization algorithm and redesigns its framework, thus improving its performance. First, a two-stage learning strategy is presented, which balances the exploration and exploitation capabilities of the particle by learning edge structures and pseudo-Steiner point choices. Especially in the second stage, a hybrid crossover strategy is designed to guarantee convergence quality. Second, the competition mechanism is adopted to select particle learning objects and enhance diversity. Finally, according to the characteristics of the discrete TD-XSMT problem, the mutation and crossover operators of the genetic algorithm are used to effectively discretize the proposed algorithm. Experimental results reveal that TSCPSO-TD-XSMT can obtain a smooth trade-off between wirelength and maximum source-to-sink pathlength, and achieve distinguished timing delay optimization.
The new 7nm Artificial Intelligence (AI) chip is an important milestone recently announced by the IBM research team, with a very important optimization goal of performance. This chip technology can be extended to various business scenarios in the Internet of Things. As the basic model for Very Large Scale Integration (VLSI) routing, the Steiner minimal tree can be used in various practical problems, such as wirelength optimization and timing closure. Further considering the X-architecture and the routing resources within obstacles, an effective performance-driven X-architecture routing algorithm for AI chip design in smart manufacturing is proposed to improve the delay performance of the chip. Firstly, a special particle swarm optimization algorithm is presented to solve the discrete length-restricted X-architecture Steiner minimum tree problem in combination with genetic operations, and a particle encoding scheme is presented to encode each particle into an initial routing tree. Secondly, two look-up tables based on pins and obstacles are established to provide a fast information query for the whole algorithm flow. Thirdly, a strategy of candidate point selection is designed to make the particles satisfy the constraints. Finally, a refinement strategy is implemented to further improve the quality of the final routing tree. Compared with other state-of-the-art algorithms, the proposed algorithm achieves a better total wirelength, which is an important index of performance, thus better satisfying the demand for delay performance of AI chip design in smart manufacturing.
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