A central issue of nanoelectronics concerns their fundamental scaling limits, that is, the smallest and most energy-efficient devices that can function reliably. Unlike charge-based electronics that are prone to leakage at nanoscale dimensions, memory devices based on phase change materials (PCMs) are more scalable, storing digital information as the crystalline or amorphous state of a material. Here, we describe a novel approach to self-align PCM nanowires with individual carbon nanotube (CNT) electrodes for the first time. The highly scaled and spatially confined memory devices approach the ultimate scaling limits of PCM technology, achieving ultralow programming currents (~0.1 μA set, ~1.6 μA reset), outstanding on/off ratios (~10(3)), and improved endurance and stability at few-nanometer bit dimensions. In addition, the powerful yet simple nanofabrication approach described here can enable confining and probing many other nanoscale and molecular devices self-aligned with CNT electrodes.
Phase change memory (PCM) devices are known to reduce in power consumption as the bit volume and contact area of their electrodes are scaled down. Here, we demonstrate two types of low-power PCM devices with lateral graphene ribbon electrodes: one in which the graphene is patterned into narrow nanoribbons and the other where the phase change material is patterned into nanoribbons. The sharp graphene "edge" contacts enable switching with threshold voltages as low as ~3 V, low programming currents (<1 μA SET, <10 μA RESET) and ON/OFF ratios >100. Large-scale fabrication with graphene grown by chemical vapor deposition also enables the study of heterogeneous integration and that of variability for such nanomaterials and devices.
The Si nanowires (NWs) were contacted by focused ion beam (FIB)-deposited Pt as the Ohmic contacts. Ultralow specific contact resistivity of 1.2 × 10−6 Ω-cm2 has been measured. Due to the focused ion beam-induced amorphization of Si NWs, contact behavior is explained by diffusion theory, allowing accurate estimation of electron concentration, electron mobility, effective barrier height, and ideality factor. This study can be the guidance to correct measurement and understanding of the contact transport, which is useful for NWs device design and fabrication.
Manipulating materials at the nanometer scale is challenging, particularly if alignment with nanoscale electrodes is desired. Here we describe a lithography-free, self-aligned nanotrench ablation (SANTA) technique to create nanoscale "trenches" in a polymer like poly(methyl) methacrylate (PMMA). The nanotrenches are self-aligned with carbon nanotube (CNT) and graphene ribbon electrodes through a simple Joule heating process. Using simulations and experiments we investigate how the Joule power, ambient temperature, PMMA thickness, and substrate properties can improve the spatial resolution of this technique. We achieve sub-20 nm nanotrenches for the first time, by lowering the ambient temperature and reducing the PMMA thickness. We also demonstrate a functioning nanoscale resistive memory (RRAM) bit self-aligned with a CNT control device, achieved through the SANTA approach. This technique provides an elegant and inexpensive method to probe nanoscale devices using self-aligned electrodes, without the use of conventional alignment or lithography steps.
Data storage based on phase change materials (PCMs) encodes information as the crystalline or amorphous state of the material bit, which have a resistivity ratio >10 3 . PCM resistive storage is thought to be more scalable [1] than charge-based devices like Flash, which are prone to leakage at nanoscale dimensions. However, PCM technology has historically suffered from relatively high (~0.5 mA) programming currents [2] needed to change the phase of the material bit through Joule heating.Here, we describe PCM nanowires (NWs) that are self-aligned with carbon nanotube (CNT) electrodes, achieving switching currents of the order ~1 μA, over two orders of magnitude below industrial state of the art. Such devices confine the PCM bit in three-dimensions, unlike previous efforts with CNT electrodes [3][4][5], and approach the fundamental scaling limits of this technology. To self-align NWs with CNTs without complex lithography, we first cover CNT devices with a thin (~50 nm) layer of PMMA (Figs. 1a-c). We flow current in the CNT such that its Joule heating [3] causes the PMMA covering it to evaporate [5], leaving behind a nanotrench (Figs. 1d-e). We create nanogaps in the exposed CNT by electrical breakdown ( Fig. 1f) [4], sputter ~10 nm of Ge 2 Sb 2 Te 5 (GST) then lift-off the remaining PMMA; this leaves behind a PCM NW perfectly aligned with the two CNT electrodes (Figs. 1g-i). Figure 2a shows current-voltage (I-V) characteristics of a typical device under dc current sweep, demonstrating SET switching from the high resistance amorphous phase of the bit (R OFF ~ 2.5 GΩ) to the low-resistance crystalline state (R ON ~ 1.3 MΩ). The SET switching is initiated at a threshold voltage (V T ) through a field-induced transition of the amorphous phase; Joule heating then heats up and crystallizes the bit (at ~150 ºC) into the conductive state. The V T of our devices decreases by 20-30% after the first few switching cycles, such "burn-in" being consistent with previous reports [5]. Reversible memory switching is achieved with pulsed operation (Fig. 2b). The bit is re-amorphized (RESET) with a ~100 ns current pulse which heats up the crystalline GST to its melting point (~620 ºC) then quenches it back to a disordered amorphous GST state during the short falling edge of the pulse. A memory endurance test (Fig. 2c) shows that the device can be reversibly programmed for nearly 1500 cycles. We note that such devices are capped by a thin (~10 nm) layer of SiO 2 , which protects the GST from oxidation; however, the capping and passivation of such devices are not yet optimized and could be improved.We plot the R ON and R OFF of 102 self-aligned PCM NW devices against their respective V T in Fig. 3. The mean ratio R OFF /R ON is ~ 900 for all measured devices. A few devices have off/on ratio ~2000, approaching the intrinsic switching limits of the GST material resistance. Such a high off/on ratio has not been previously achieved, and it is very promising for multilevel memory applications even at the most reduced bit dimensions. Figure 4...
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