Organic neuromorphic computing/sensing platforms are a promising concept for local monitoring and processing of biological signals in real time. Neuromorphic devices and sensors with low conductance for low power consumption and high conductance for low‐impedance sensing are desired. However, it has been a struggle to find materials and fabrication methods that satisfy both of these properties simultaneously in a single substrate. Here, nanofiber channels with a self‐formed ion‐blocking layer are fabricated to create organic electrochemical transistors (OECTs) that can be tailored to achieve low‐power neuromorphic computing and fast‐response sensing by transferring different amounts of electrospun nanofibers to each device. With their nanofiber architecture, the OECTs exhibit a low switching energy of 113 fJ and operate within a wide bandwidth (cut‐off frequency of 13.5 kHz), opening a new paradigm for energy‐efficient neuromorphic computing/sensing platforms in a biological environment without the leakage of personal information.

Nonvolatile memory (NVM)‐based neuromorphic computing has been attracting considerable attention from academia and the industry. Although it is not completely successful yet, remarkable achievements have been reported pertaining to synaptic devices that can leverage NVM capable of storing multiple states. The analog synaptic devices performing computation similar to biological nerve systems are crucial in energy‐efficient analog neuromorphic computing systems. To use NVM as an analog synaptic device, researchers focus on improving device characteristics. Among various characteristics, the most challenging one is linearity and symmetry of synaptic weight update that is required for on‐chip training. In this regard, this review paper discusses recent synaptic device improvements focusing on novel schemes tailored for each NVM device to improve the linearity and symmetry. In addition to device‐level studies, recent research achievements are reviewed expanded up to chip‐level studies because in realizing neuromorphic hardware systems beyond a single synaptic device, several considerations and requirements are needed to confirm for high‐level design, and accordingly, cooptimize among synaptic devices, synapse arrays, electrical circuits, neural networks, algorithms, and implementation. Also, this review paper introduces various circuit and algorithmic approaches to compensate for the non‐ideality of the analog synaptic device.