We investigated the threshold voltage (Vth) instability for various gate dielectrics (SiNx and SiOx) in amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs). The a-IGZO TFTs with SiNx 150 °C exhibited reasonable electrical performance (field-effect mobility of 8.1 cm2/V s and Ion/off ratio of >108) but showed huge Vth shift under positive gate bias. The TFTs with SiOx dielectrics exhibit smaller Vth instability than those of SiNx dielectrics. This behavior can be explained by using simple charge trapping into the gate insulators and the difference of Vth instability on various dielectrics may be originated from the hydrogen contents, providing high density of charge traps in gate dielectrics.

The electrical instability in thin-film transistors ͑TFTs͒ based on amorphous indium-gallium-zinc oxide ͑a-IGZO͒ was investigated using constant bias and constant current stress. Stress conditions were chosen such that TFT is turned on, whereas the potential at the gate dielectric-a-IGZO interface is below the electron accumulation threshold. Drain current in this low bias regime is still sufficient for driving pixels in an organic light-emitting diode display ͑AMOLED͒. We found that the degradation is due to charge trapping near the a-IGZO-gate dielectric interface. The obtained results enabled a straightforward assessment of a-IGZO TFTs' instability for their application in AMOLEDs.Thin-film transistors ͑TFTs͒ based on ͑transparent͒ metal oxide semiconductors 1,2 have recently attracted much attention for applications in flat-panel displays such as liquid-crystal displays, 3 electrophoretic displays, 4 and especially organic light-emitting diode displays ͑AMOLEDs͒. 5 Amorphous In-Ga-Zn oxide ͑a-IGZO͒ TFT back-planes were of particular interest because good device performance and good spatial uniformity of electrical parameters can be achieved with a conventional bottom-gate staggered structure in a simple manufacturing process. 5 Reliable data on TFT degradation and an understanding of the degradation mechanisms under operation-bias conditions are required for the design and manufacture of display devices. According to previous reports on electrical instabilities in a-IGZO TFTs, the magnitudes of measured threshold voltage shifts varied depending on active layer thickness, 6 gate dielectric, 7 and channel passivation layer. 8 Theoretical studies suggest that, in contrast to Si-based TFTs, trap generation is unlikely in oxide semiconductors due to the absence of weak covalent bonds and the inability of interstitial hydrogen to initiate bond rearrangements. 9 Charge trapping in the gate dielectric or at the semiconductor-gate dielectric interface 10 and charge transfer from the semiconductor to the adsorbed molecules at the back-channel interface 8 were suggested to be the mechanisms of the degradation. The strong arguments that support the latter come from the effect of the passivation layer on TFT instability 8 and from the effects of oxygen ambient 11 and humidity 12 on the characteristics of unpassivated a-IGZO TFTs. However, high stress gate-bias values well above those that are practically required were used in previous reports.In this article, we report the bias-and current-stress characterizations of electrical instability in a-IGZO TFTs biased below the accumulation threshold at the gate dielectric-a-IGZO interface. The TFT drain current in this low bias regime is still sufficient for driving AMOLED pixels. Charge trapping in the gate dielectric is unlikely to dominate the degradation at low gate bias. To identify the location of the trapped charge, we estimated flatband voltage shifts due to charge trapping in the a-IGZO layer and both of its interfaces and compared the calculated values with those from...