Abstract-Channel emulators are valuable tools for controllable and repeatable wireless experimentation. Often, however, the high cost of such emulators preclude their widespread usage, especially in large-scale wireless networks. Moreover, existing channel emulators offer either very realistic channels for simplistic topologies or complex topologies with highly-abstracted, lowfidelity channels. To bridge the gap in offering a low-cost channel emulation solution which can scale to a large network size, in this paper, we study the tradeoff in channel emulation fidelity versus the hardware resources consumed using both analytical modeling and FPGA-based implementation. To reduce the memory footprint of our design, we optimize our channel emulation using an iterative structure to generate the Rayleigh fading channel. In addition, the channel update rate and word length selection are also evaluated in the paper which greatly improve the efficiency of implementation. We then extend our analysis of a single channel to understand how the implementation scales for the emulation of a large-scale wireless network, showing that up to 24 vehicular channels can be emulated in real-time on a single Virtex-4 FPGA.
In this work, we optimize hardware consumption in Rayleigh channel generation. Due to the advantage in saving memory resource, a recursive-structure-based channel generator is considered in this paper. We first investigate the long-term accuracy of channel generation by the recursive structure. Afterwards, we calculate the optimum bit width and channel update period at which normalized mean-square-error (MSE) minimization is achieved. The minimization is under a constraint of a upper bound on a bit rate which is defined as the ratio of bit width over channel data update period. Via experiments on a Xilinx FPGA chip, the optimization in the generation of Rayleigh channel with U -shaped spectrum saves more than 31% bit rate for the normalized MSE of 1.8 × 10 −6 . According to our experiments, the 31% bit rate reduction can save up to 174 slices, 31 flip-flops, and 390 LUTs.Index Terms-Fading channel generator, field-programmable gate array (FPGA), joint optimization over sampling period and bits, stability of an iterative structure based sinusoid generator, sum of sinusoids.
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