Affinity purified anticardiolipin antibodies (ACLA) raised in rabbits showed cross-reactivities with various negatively charged phospholipids as shown by both the solid phase enzyme-linked immunosorbent assay (ELISA) and inhibition studies. In ELISA, ACLA showed strong cross-reactivity to both sphingomyelin (SM) and phosphatidylethanolamine (PE), but the inhibition studies showed that ACLA failed to bind the aqueous suspensions of SM, PE, and PE/PC (1:1). ACLA bound to resting gel-filtered human platelets (GFP) as shown by both inhibition study and flow cytofluorometric analysis. Western blotting procedure showed that ACLA strongly cross-reacted to an 80-Kd plasma membrane protein. ACLA activated platelet response in a concentration-dependent manner. At less than 10 micrograms/mL, ACLA induced both platelet shape change to spiculate irregular forms as shown by scanning electron microscopy and the phosphorylation of 20-Kd protein. ACLA at more than 10 micrograms/mL caused platelet aggregation and secretion. The aggregation was inhibited by EDTA; aspirin; antimycin A plus 2-deoxyglucose; PGE1; and the F(ab')2 fragment of ACLA. It was not inhibited by monoclonal antibody to Fc receptor (MoAb FcR2). The biochemical events of ACLA-induced platelet response involved the elevation of (1) thromboxane A2 formation, (2) cytosolic free calcium ion concentration ([Ca2+]i), and (3) 47-Kd protein phosphorylation. In addition, the subaggregatory concentration of ACLA showed synergistic platelet activation with that concentration of thrombin, collagen, and epinephrine. The study showed the mechanism involved in ACLA-induced platelet responses.
-We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant saving in filtering time, local memory usage, and memory traffic. Every 16x16 macroblock requires 192 filtering operations. After a few initialization cycles, our 5-stage pipelined architecture is able to perform one filtering operation per cycle. Compared with some state-of-the-art designs, our architecture delivers the fastest level of performance while using much smaller gate count and memory. We have implemented and integrated the proposed deblocking filter into an H.264 main profile video decoder and verified it with an FPGA prototype.
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