Reed-Solomon erasure codes (RS-EC) are widely used in packet communication and storage systems to recover erasures. When the RS-EC decoder is implemented on a FieldProgrammable Gate Array (FPGA) in a space platform, it will suffer Single Event Upsets (SEUs) that can cause failures. In this paper, the reliability of an RS-EC decoder implemented on an FPGA when there are errors in the user memory is firstly studied. Then a fault detection and localization scheme is proposed based on partial re-encoding for the faults in user memory of the RS decoder. Furthermore, check bits are added in the generator matrix to improve the fault location performance. Theoretical analysis shows that the scheme could detect most faults with small missing and false detection probability. Experimental results on a case study show that more than 90% faults on user memory could be tolerated by the decoder, and the all other faults can be detected by the fault detection scheme when the number of erasures is less than the correction capability of the code. Although false alarms exist (with probability smaller than 4%), they can be used to avoid faults accumulation. Finally, the fault location scheme could accurately locate all the faults. The theoretical estimates are very close to the experiment results, which verifies the correctness of the analysis done.
Low Density Parity Check (LDPC) codes are used in 5G systems for traffic channels due to their excellent error correction capability for long sequences, and the Min-Sum algorithm is widely applied in practical implementations of LDPC decoders due to its low complexity. If the decoder is implemented on a SRAM-based field-programmable gate array (SRAM-FPGA), the radiation-induced single-event upsets (SEUs) can affect the operation of the LDPC decoder by corrupting the configuration memory, which can change the circuit functionality and will not be corrected unless the FPGA is reconfigured. Therefore, protection of LDPC decoders with low overhead is an important problem, especially for resource-limited on-board space systems. In this paper, an efficient Duplicate With Comparison (DWC) protection scheme is proposed based on the different distribution of the parity check sum of the LDPC decoder in the error-free case and the faulty case. In particular, the check sum accumulation number and threshold are optimized to achieve high detection probability with short delay. FPGA based implementation and hardware fault injection experiments are conducted to evaluate the performance of the proposed schemes.Experimental results show that, the effect of SEUs on the LDPC decoder can be completely eliminated by the proposed scheme with 2x times computational overhead and 1.69x times power consumption overhead compared to the unprotected decoder.
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