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A new static CMOS differential logic based on multiple-input floating-gate MOS (FGMOS) transistor is proposed. In this circuit configuration, a pair of n-channel multiple-input FGMOS pull down networks is used to replace the nMOS logic tree in the conventional cascode voltage switch logic (CVSL) circuit in order to simplify the circuit structure. By using the advantage that voltage signals are easy to be added by means of floating gate in multiple-input FGMOS transistor, a simple synthesis technique of the n-channel multiple-input FGMOS logic tree by employing summation signal is also discussed. On the basis of the proposed synthesis method, some logic circuits including full adder are designed. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology with a power supply of 1.5V is utilized to validate the effectiveness of the proposed logic circuits.

Data stability, power consumption and delay are important issues with the scaling of CMOS technology. An asymmetric eight-transistor SRAM cell with improved static-noise margin (SNM) is proposed. In this new 8T SRAM cell, unilateral reading mechanism and dynamic power scheme are combined. Results are validated by HSPICE simulation using 45nm PTM model. The simulated results of the SNM, the power consumption, the propagation delay and the power delay product (PDP) are compared between the dynamic power 6T SRAM cell and the proposed 8T SRAM cell.

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