Using molecular dynamic simulations for the melting transition of a flux line lattice(FLL) with point disordered pinnings, thermal fluctuations and magnetic interactions between pancake vortices, we study the disorder-driven melting transition from a disentangled and ordered Bragg glass (BG) to an entangled amorphous vortex glass (VG) or a vortex liquid (VL) in the pinning strength-temperature phase diagram. A portion of the BG region is found to be sandwiched in between the VG phase at lower temperatures and VL phase at higher temperatures, exhibiting inverse melting behavior observed recently on BSCCO crystals.
We develop a three-dimensional flux line lattice model in the layered superconductors, taking into account both long-range magnetic interactions between pancake vortices located in different layers for a single flux line and those between vortices located in the same layer for different flux lines. Using Langevin dynamic simulations, we study the disorder and thermally driven melting transitions from a disentangled Bragg glass ͑BG͒ with quasi-long-range order to an entangled amorphous vortex glass ͑VG͒ or a vortex liquid ͑VL͒ in the disorder strength-temperature phase diagram. Owing to nonmonotonous temperature dependence of the interactions between vortices, the BG-VG melting line exhibit unusual temperature behavior, reproducing the inverse melting phenomenon observed recently on BSCCO crystals.
This paper describes cellular automata simulation techniques used to predict the anisotropic etching of single-crystal silicon. In particular, this paper will focus on the application of wet etching of silicon wafers using typical anisotropic etchants such as KOH, TMAH, and EDP. Achieving a desired final 3D geometry of etch silicon wafers often is difficult without requiring a number of fabrication design iterations. The result is wasted time and resources. AnisE, a tool to simulate anisotropic etching of silicon wafers using cellular automata simulation, was developed in order to efficiently prototype and manufacture MEMS devices. AnisE has been shown to effectively decrease device development time and costs by up to 50% and 60%, respectively.
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