The characteristics of near interface electron and hole traps in n-type 4H-SiC MOS capacitors with and without nitric oxide (NO) passivation have been systematically investigated. The hysteresis of the bidirectional capacitance-voltage (C-V) and the shift of flat band voltage (Vfb) caused by bias stress (BS) with and without ultraviolet light (UVL) irradiation are used for studying the influence of near interface electron traps (NIETs) and near interface hole traps (NIHTs). Compared with Ar annealed process, NO passivation can effectively reduce the density of NIETs, but induce excess NIHTs in the SiC MOS devices. What’s worse is that part of the trapped hole cannot be released easily from the NIHTs in the NO annealed sample, which may act as the positive fixed charge and induce the negative shift of threshold voltage.
Even with SiC power MOSFETs released into the commercial market, the threshold voltage instability caused by near interface states is still an attracting issue, which is a major obstacle to further improving the device performance. In this paper, the effects of temperature storage on the threshold voltage stability of n-channel 4H-SiC VDMOSFET are studied. It is found that the capture of hole traps is dominant during the long-term temperature storage at 425 K, causing a considerable negative shift of threshold voltage. In view of the influence of temperature storage, the positive and negative drift trends of threshold voltage slow down during the gate-bias stress measurement. And the ∆VTH, the difference between the threshold voltages recorded after positive and negative gate-bias stress in the same duration, also grows slowly with the increasing stress duration. Finally, some suggestions for improving the threshold reliability of n-channel SiC VDMOSFETs are presented.
This paper proposes a new structure of 4H-SiC bipolar junction transistor, which can both achieve high current gain and high open base breakdown voltage. By introducing a groove type of metal-high k dielectric-silicon carbide (MIS) structure into the active region along the base-emitter sidewall which is formed with the process of isolation etching, a large electric field appears at the interface between high-k dielectric and bulk material by analyzing the potential distribution in forward mode, thus accelerating the electron transport. Based on a doping concentration of 4×1017cm-3and thickness of 0.6um base region, current gain of as high as 191 is obtained using TCAD simulation, and that is almost double of the conventional structure in the same simulation setup. Furthermore, a field plate structure is composed combined with the base contact metal simultaneously, and the open base breakdown voltage is obviously increased from 634V to 948V with a 6μm-thick n-SiC collector (Nd=3×1015cm-3).
This paper investigated a feasible process of growing epitaxial graphene on 4H hexagonal poly-type of silicon carbide Si-faced polar surface (0001) under an argon pressure of 900 mbar conditions. Using Raman Spectroscopy, Scanning Electron Microscopy and X-ray Photoelectron Spectroscopy, epitaxial graphene grown at temperature 1600°C is confirmed to take shape weakly on 4H-SiC (0001) with an average domain size of several tens of nanometers, and this can be seen as the characteristic of initial formation of epitaxial graphene on substrate.
In this paper, an improved planar MOS barrier Schottky (PMBS) rectifier is proposed which utilizes the PECVD deposited high-k semi-insulating polycrystalline silicon (SIPOS) as the MOS area gate dielectrics for the first time. By adopting the high-k SIPOS as the MOS gate dielectrics, the peak electric field at the interface betwwen dielectrics layer and SiC can be significantly relieved and the device reliability can obviously enhanced without considerable degradation of on-state characteristics. With the optimized the thickness of the SIPOS film, the breakdown voltage (BV) of 1500V for the fabricated device was achieved, which is approximately corresponds to 85% of the theoretical parallel plane breakdown voltage value calculated from the used epilayer structure. And the specific on-state resistance (RSP-ON) is about 4.2mΩ•cm2. The corresponding figure-of-merit of VB2/ RSP-ON for the proposed device is 535.7MW/cm2.
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