Hardware acceleration of deep learning using analog non-volatile memory (NVM) requires large arrays with high device yield, high accuracy Multiply-ACcumulate (MAC) operations, and routing frameworks for implementing arbitrary deep neural network (DNN) topologies. In this article, we present a 14-nm test-chip for Analog AI inference-it contains multiple arrays of phase change memory (PCM)devices, each array capable of storing 512 × 512 unique DNN weights and executing massively parallel MAC operations at the location of the data. DNN excitations are transported across the chip using a duration representation on a parallel and reconfigurable 2-D mesh. To accurately transfer inference models to the chip, we describe a closed-loop tuning (CLT) algorithm that programs the four PCM conductances in each weight, achieving <3% average weighterror. A row-wise programming scheme and associated circuitry allow us to execute CLT on up to 512 weights concurrently. We show that the test chip can achieve near-software-equivalent accuracy on two different DNNs. We demonstrate tile-to-tile transport with a fully-on-chip two-layer network for MNIST (accuracy degradation ∼0.6%)

This paper presents a new type of wireless networking applications in data centers using steered-beam mmWave links. By taking advantage of clean LOS channels on top of server racks, robust wireless packet-switching network can be built. The transmission latency can be reduced by flexibly bridging adjacent rows of racks wirelessly without using long cables and multiple switches. Eliminating cables and switches also reduces equipment costs as well as server installation and reconfiguration costs. Security can be physically enhanced with controlled directivity and negligible wall penetration. The aggregate data transmission BW per given volume is expected to scale as the fourth power of carrier frequency. The paper also deals with the architecture of such network configurations and a preliminary demonstration system.

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