Among the tenets of Smart Manufacturing (SM) or Industry 4.0 (I4.0), digital twin (DT), which represents the capabilities of virtual representations of components and systems, has been cited as the biggest technology trend disrupting engineering and design today. DTs have been in use for years in areas such as model-based process control and predictive maintenance, however moving forward a framework is needed that will support the expected pervasiveness of DT technology in the evolution of SM or I4.0. A set of requirements for a DT framework has been derived from analysis of DT definitions, DTs in use today, expected DT applications in the near future, and longer-term DT trends and the DT vision in SM. These requirements include elements of re-usability, interoperability, interchangeability, maintainability, extensibility, and autonomy across the entire DT lifecycle. A baseline framework for DT technology has been developed that addresses many aspects of these requirements and enables the addressing of the requirements more fully through additional specification. The baseline framework includes a definition of a DT and an object-oriented (O-O) architecture for DTs that defines generalization, aggregation and instantiation of DT classes. Case studies using and extending the baseline framework illustrate its advantages in supporting DT solutions and trends in SM.

Safety violations in programmable logic controllers (PLCs), caused either by faults or attacks, have recently garnered significant attention. However, prior efforts at PLC code vetting suffer from many drawbacks. Static analyses and verification cause significant false positives and cannot reveal specific runtime contexts. Dynamic analyses and symbolic execution, on the other hand, fail due to their inability to handle real-world PLC programs that are event-driven and timing sensitive. In this paper, we propose VETPLC, a temporal context-aware, program analysisbased approach to produce timed event sequences that can be used for automatic safety vetting. To this end, we (a) perform static program analysis to create timed event causality graphs in order to understand causal relations among events in PLC code and (b) mine temporal invariants from data traces collected in Industrial Control System (ICS) testbeds to quantitatively gauge temporal dependencies that are constrained by machine operations. Our VETPLC prototype has been implemented in 15K lines of code. We evaluate it on 10 real-world scenarios from two different ICS settings. Our experiments show that VETPLC outperforms state-of-the-art techniques and can generate event sequences that can be used to automatically detect hidden safety violations.

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Digital Twin (DT) is an emerging technology that has recently been cited as an underpinning element of the digital transformation. DTs are commonly defined as digital replicas of components, systems, products, and services that receive data from the field to support intelligent decision-making. Although several frameworks for DT application in manufacturing have been proposed, there is no systematic methodology in the literature that supports the development of scalable, reusable, interoperable, interchangeable, and extensible DT solutions, while taking into account specific manufacturing environment needs and conditions. This paper introduces a DT solution development methodology as a generic procedure for analyzing and developing DTs for manufacturing systems. The methodology is based on the well-known System Development Life Cycle (SDLC) process and takes into consideration: (1) the specificity of DT characteristics and requirements, (2) an understanding of the manufacturing context in which the DTs will operate, and (3) the object-oriented aspects required to achieve DT capabilities of scalability, reusability, interoperability, interchangeability, and extensibility. A case study illustrates the advantages of the proposed methodology in supporting manufacturing DT solutions.

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