High efficient implementation of scaling in residue number system (RNS) is one of the critical issues for the applications of RNS in digital signal processing (DSP) systems. In this paper, an efficient scaling algorithm for signed integers in RNS is proposed firstly through introducing a correction constant in negative integers scaling procedure. Based on the proposed scaling algorithm, an efficient RNS 2 n scaling implementation method is presented, in which Chinese remainder theorem (CRT) and a redundant modulus are used to perform the base extension to obtain the least significant n bits of RNS integers. With the redundant modulus, the RNS sign detection can be achieved by the parity detection. And then, an approach to update the residue digit of the redundant channel is also proposed. Meanwhile, this paper provides a method of computing the correction constant of the redundant channel in negative integers scaling. The analysis results indicate that the complexity of the proposed scaling algorithm grows linearly with the word-length of the RNS dynamic range without using Look-up Table (LUT). Furthermore, the proposed algorithm is employed for a specific moduli set 2 n scaling. The synthesis results show that the critical path of the proposed algorithm is shortened by 12%, the area and power consumption performance is improved by about 35%, compared to the existing cascading 2 n scaling method for very large scale integration (VLSI) implementation under the same restriction. Besides, the VLSI layout indicates that the parallel structure is simpler. CitationMa S, Hu J H, Ye Y L, et al. A 2 n scaling scheme for signed RNS integers and its VLSI implementation.
The high efficient of scaling operation for Residue Number System (RNS) with VSLI implementation plays an important role in RNS-based information processing systems. With the properties of moduli set {2 1, 2 , 2 1} n n n , we propose an efficient 2 n scaling scheme for this moduli set. Furthermore, the corrective factor for scaling a negative number is also introduced. The analysis shows that the proposed scaler has high area and power consumption performances compared to the cascading scaling scheme. The scaler can be used in the design of RNS-based ALUs and DSP systems.
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