To achieve both low power consumption and high-speed operation, we fabricated c-axis-aligned crystalline indium–gallium–zinc oxide (CAAC-IGZO) field-effect transistors (FETs) with In-rich IGZO and common IGZO (
in atomic ratio) active layers through a simple process using trench gates, and evaluated their characteristics. The results confirm that 60-nm-node IGZO FETs fabricated through a 450 °C process show an extremely low off-state current below the detection limit (at most 2 × 10−16 A) even at a measurement temperature of 150 °C. The results also reveal that the FETs with the In-rich IGZO active layer show a higher on-state current than those with the common IGZO active layer and have excellent frequency characteristics with a cutoff frequency and a maximum oscillation frequency of up to 20 and 6 GHz, respectively. Thus, we demonstrated that CAAC-IGZO FETs with trench gates are promising for achieving both low power consumption and high-speed operation.
Hardware is required to be further miniaturized aiming at advancement of the Internet of things and artificial intelligence. Widely used Si transistors, which have achieved miniaturization on the order of 10 nm, are apparently difficult to further miniaturize, and stacking techniques have been developed as a breakthrough. Our IGZO FETs have a gate length of 6.8 nm or less owing to the wide band gap of IGZO and an optimized transistor structure, and can be highly integrated by a contact formation technique.
We report here a novel integrated passive substrate by using thin film technology directly fabricated on a multi-layer laminates. The thin film part consists of electroplated Cu interconnect and low-loss BCB dielectric fabricated on flattened PPE laminated substrate. According to microstripbased approaches, the structures of an inductor, capacitor and resistor were optimized and a very high-Q inductors and capacitors were obtained. The separating routing design scheme between the thin film part and the multi-layer laminate part makes the RF-module compact and shows superior isolation performance.
IntroductionSystem-level-packaging technology (SIP: System in Package) is receiving attention because it can reduce system cost, size and time-to-market. In particular, a RF-front-end block with a large number of passive components and RF components is a candidate for the SIP. To realize compact and cost-effective RF-front-ends in future-broadband wireless system, an integration technology for these RF-components is one of the key issues.However passive components
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