In some applications the observed samples are inherently nonuniform. In contrast to that in this paper we take advantage of deliberate nonuniform sampling and perform DSP where the classical approaches leave off. For instance think about mobile communication or digital radio. Deliberate nonuniform sampling promises increased equivalent sampling rates with reduced overall hardware costs. The equivalent sampling rate is the sampling rate that a uniform sampling device would require in order to achieve the same processing bandwidth. While the equivalent bandwidth of a realizable system may well extend into the GHz range its mean sampling rate is usually in the MHz range. Current existing prototype systems achieve 40 times the bandwidth of a classic DSP system that would operate uniformly (cf. [3] and [4]). Throughout the literature on nonuniform sampling (e. g.[I], [2] and [SI) many sampling schemes have been investigated. In this paper the authors discuss a nonuniform sampling scheme that is especially suited to be implemented in digital devices, thus, fully exploiting state-of-the-art ADCs without violating their specifications. An analysis of the statistical properties .of the algorithm is given to demonstrate common pitfalls and to prove its correctness.
Deliberate nonuniform sampling promises increased equivalent sampling rates with reduced overall hardware costs of the DSP system. The equivalent sampling rate is the sampling rate that a uniform sampling device would require in order to achieve the same processing bandwidth. Equivalent bandwidths of realizable systems may well extend into the GHz range while the mean sampling rate stays in the MHz range. Current prototype systems (IECS) have an equivalent bandwidth of 1.6GHz at a mean sampling rate of 80MHz, achieving 40 times the bandwidth of a classic DSP system that would operate uniformly at 80MHz (cf. [ 11). Throughout the literature on nonuniform sampling (e. g.[2] and [3]) different sampling schemes have been investigated. This paper focuses on nonuniform sampling schemes optimized for fast and efficient hardware implementations. To our knowledge this is the first proposal of an efficient nonuniform sampling driver (SD) design in the open literature.
Currently the high-precision event timers represent powerful tools for time measurement in various applications, including jitter measurement. Applied potential of this technology is illustrated by the example of clock jitter measurement and analysis based on the application of a high-precision event timer. The basic measurement procedures resulting in estimations of commonly used jitter parameters (such as accumulated jitter, period jitter, clock-to-clock jitter) are discussed. An approach to informal interpretation of statistical jitter characteristics based on theoretical jitter model and results of computer simulation is offered. Experimental results of jitter measurement and analysis for high-precision clock oscillators confirm the assumption that currently the event timing can provide for jitter measurement precision comparable with traditional oscilloscope-based techniques.
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