Several new building blocks are demonstrated, which enable low-power (1.1-1.8V) analog functionality in a single-poly, digital CMOS process. These cells facilitate the integration of analog converters on system-on-a-chip IC's without adding any extra cost to the process. A voice A/D, designed with these circuits, exhibited an SNR of 68 dB at an analog supply voltage of 1.1V, and 75dB at 1.8V. This is despite the noisy digital environment of an on-chip DSP operating at 60 Mhz and a digital supply voltage of 2.5V. INTRODUCTIONThere has recently been an increasing need to develop system-on-a-chip capability. This presents a special challenge for the design of analog blocks, since the switching noise on high frequency digital chips can severely degrade analog performance at the transistor and building block level. Futhermore, in many applications, such as DSP's and microcontrollers for wireless systems, the tendency has been to save power in the digital part by reducing the supply voltage (1.8V in the next generation). This complicates integrated analog functions, since many of the analog methods, such as stacked Vt's, can not be utilized. The low power requirement also requires a reduction in the VDSAT values, which makes the transistors more sensitive to digital noise. The conflicting requirements of low power and switching noise immunity make designing analog circuits an especially difficult task. Thus, the realization of analog functions integrated onto digital chips requires a rethinking of many of the analog building blocks.Motorola has recently reported a DSP with an integrated voice codec which was fabricated with a standard digital CMOS process [1]. This process had no special analog additions, such as double-poly or salicide block. It thus utilized non-linear MOS capacitors and non-linear nwell resistors. Usage of a "pure" digital process makes the analog integration significantly more cost-effective, since in system IC's the analog part accounts for typically 3-5% of the area, and the added cost of the analog process (i.e. double poly and salicide block) would be imposed on the entire chip. In addition, the digital processes typically are qualified 6 months -1 year before the analog processes. Thus, using a digital process improves the time-to-market when the IC's have an aggressive shrink path.The analog part of this chip was functional down to 1.1V, and was highly insensitive to the digital noise while the DSP was operating at 60 MHz. In this paper, the circuit design approach for this technology, and its analog building blocks are reported for the first time. ARCHITECTURE AND BUILDING BLOCKSIn standard sigma-delta converters, switched capacitor techniques are generally utilized. However, these types of methods are very deficient in the presence of digital noise. This is because a voltage is being sampled at a specific time point. Digital spikes are also sampled at this time and can be aliased back into the pass-band, causing a degradation of the analog performance. In the approach discussed her...
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