The existing directions-of-arrival (DOAs) estimation methods for two-dimensional (2D) coherently distributed sources need one-or two-dimensional search, and the computational complexities of them are high. In addition, most of them are designed for special angular signal distribution functions. As a result, their performances will degenerate when deal with different sources with different angular signal distribution functions or unknown angular signal distribution functions. In this paper, a low-complexity decoupled DOAs estimation method without searching using two parallel uniform linear arrays (ULAs) is proposed for coherently distributed sources, as well as a novel parameter matching method. It can resolve the problems mentioned above efficiently. Simulation results validate the effectiveness of our approach.2D coherently distributed source, uniform linear array, direction-of-arrival (DOA), decoupled estimation, quadric rotational invariance property (QRIP)
The implementation of a high-speed low-power pulse swallow frequency divider for a DRM/DAB frequency synthesizer, using a 0.18-μm CMOS technology, is described. The frequency divider employs a divide-by-32/33 dual-modulus prescaler, a five bits swallow counter, an 11 bits programmable counter, and a control circuit necessary for the time sequence and operation of the division. In the pulse swallow frequency divider, the divide-by-32/33 dualmodulus prescaler consists of a divider-by-4/5 and an asynchronous divider-by-8 frequency divider, the swallow counter and the programmable counter consist of static-logic fall edge-triggered DFFs. The structure is designed to reduce the power consumption. Post-simulated results show that the programmable divider's operation frequency is from 0.5 GHz to 3.5 GHz with a maximum power consumption of 3.01 mW at 1.8V power supply. The dimension of pulse swallow frequency divider is 270 μm×110 μm.
This paper presents a low-power CMOS receiving signal strength indicator (RSSI). The main architecture of the circuit adopts a six-stage limiting amplifier (LA) in a logarithmic-linear form, which shows a good performance in weak signal detection. The RSSI achieves high tolerance to process, voltage, and temperature (PVT) variations by utilizing the unique nature of branch currents in a transconductance amplifier. The power consumption is decreased by using the weak-inversion LAs. Full-waveform current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low power consumption. Measured results show that in the 1 kHz–50 MHz frequency range, the input dynamic range is wider than 70 dB within ±2 dB linearity error. The chip occupies an area of 0.7 mm2 × 0.3 mm2 using a 0.18-μm CMOS. It draws 1.3 mA from a 1.8 V supply.
This paper describes a novel low-power wideband low-phase noise divide-by-two frequency divider. Hereby, a new D-latch topology is introduced. By means of conventional dynamic source-coupled logic techniques, the divider demonstrates a wideband with low phase noise by adding a switch transistor between the clock port and the couple node of the input NMOS pair in the D latch. The chip was fabricated in the 90-nm CMOS process of IBM. The measurement results show that the frequency divider has an input frequency range from 0.05 to 10 GHz and the phase noise is -159.8 dBc/Hz at 1 MHz offset from the carrier. Working at 10 GHz, the frequency divider dissipates a total power of 9.12 mW from a 1.2 V supply while occupying only 0.008 mm 2 of the core die area.
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