A convenient nanotechnique is used to place analyte molecules between closely spaced silver-capped Si nanowires for investigating surface-enhanced Raman scattering (SERS). It is revealed that the SERS intensity (or sensitivity) is closely related to the etching time used to prepare the Si nanowires from wafer. As the etching leaves the nominal spacing between the nanowires unaffected, the observed effect can be explained based on different gaps between the Ag particles due to the different lengths of the Si nanowires. Large SERS intensity for short etching times can be elucidated in terms of the rigidity of the nanowires and the smaller SERS intensities for longer etching times can be explained by considering the bending of nanowires and the agglomeration of the Ag caps due to gravity and van der Waals forces.

Assembling nanoscale building blocks into an orderly network with a programmable layout and channel designs represents a critical capability to enable a wide range of stretchable electronics. Here, we demonstrate the growth-in-place integration of silicon nanowire (SiNW) springs into highly stretchable, transparent, and quasicontinuous functional networks with a close to unity interconnection among the discrete electrode joints because of a unique double-lane/double-step guiding edge design. The SiNW networks can be reliably transferred to a soft elastomer substrate, conformally attached to highly curved surfaces, or deployed as self-supporting/movable membranes suspended over voids. A high stretchability of >40% is achieved for the SiNW network on an elastomer, which can be employed as a transparent and semiconducting thin-film material endowed with a high carrier mobility of >50 cm2/(V s), I on/I off ratio >104, and a tunable transmission of >80% over a wide spectrum range. Reversibly stretchable and bendable sensors based on the SiNW network have been successfully demonstrated, where the local strain distribution within the spring network can be directly observed and analyzed by finite element simulations. This SiNW network has a unique potential to eventually establish a new generically purposed waferlike platform for constructing soft electronics with Si-based hard performances.

Building 3D electronics represents a promising method for the integration of more functionalities into a given footprint. To this end, stacked multilevel silicon nanowires (SiNWs) are ideal multilevel channels to construct high‐density 3D electronics. 3D vectorial self‐assembled growth of orderly lateral SiNWs is accomplished directly upon oblique or vertical sidewalls, which are otherwise difficult to address by conventional lithography, led by indium droplets that absorb amorphous silicon thin film coated on the sidewalls to produce SiNW stacks at only 350 °C. With the guidance of sidewall terraces formed by multilayer or alternating etching approaches, ultralong supported or suspended multilevel SiNW stacks can be easily mass produced with tailored geometry and average diameter and spacing down to 50 and 100 nm, respectively. Prototype stacked multi‐SiNW‐channel transistors, with a fin‐gate configuration, are also fabricated and demonstrate an impressive high Ion/Ioff current ratio >107, a hole mobility of 60 cm2/V−1 s−1, and a rather low leakage current. These results highlight the unique potential and versatility of a nanodroplet‐assisted self‐assembled growth in constructing more complex and advanced 3D stacked channel electronics.