IndexTerms-Side-channel attack, Reconfigurable architecture, Cryptographic Coprocessor, correlation based differential analysis (CPA), electromagnetic analysis (EMA).Abstract-A secure reconfigurable cryptographic co-processor (SRCP) supporting multiple algorithms of AES, DES, RC6 and IDEA is proposed using its own reconfigurable feature to resist Side-channel attack (SCA). It is integrated into a system-on chip and fabricated in 0.18 μm CMOS process with 1.8 V supply voltage and 100 MHz max frequency. Several kinds of specific countermeasures are proposed to hide leakage information by utilizing idle reconfigurable processing elements (PEs) to do dummy operations. Its advantages lie in its little impact on area and frequency as well as high flexibility after silicon that countermeasures can also be reconfigured. Furthermore, different protections including several kinds of global countermeasures and encryption flow related countermeasures can be stacked, thus the security level can be tuned by trading for some performance or power consumption. Experimental SCA attack results show that it resists SPA and DPA without revealing the subkey. For correlation based EMA of DES configuration, it increases 36× measure to disclosure when applied with partial countermeasures compared to unprotected DES. As to AES configuration with full countermeasures, it resists EMA with no sign to reveal the right subkey for up to 1.2 million electromagnetic traces.
S-box is a core component of many block cipher algorithms. A reconfigurable S-box based on look-up table (LUT) with memory-sharing is proposed in this paper. It uses a sharing memory to support different S-box operation modes (4 × 4, 6 × 4, and 8 × 8) for most of the block cipher algorithms as well as reduce memory size. It also supports high-speed pipeline structure of DES and Serpent. This new type of S-box is applied in a reconfigurable cryptographic coprocessor under 0.18 μm CMOS process. It is also used in a DES circuit with 16 pipeline stages. Synthesis results show that it works at 100 MHz frequency with flexibility of different modes and a reduced area compared to non-memory-sharing LUT method with equivalent sizes of different S-boxes.
A side-channel analysis resistant reconfigurable cryptographic coprocessor is designed and fabricated in 0.18μm CMOS with 1.8V supply and 100MHz frequency, supporting multiple block cipher algorithms of AES, DES, RC6 and IDEA. Our countermeasure utilizes idle processing elements existed in reconfigurable array to do dummy operations to hide leakage information. This method has little impact on area and frequency, and it is flexible after silicon. It resists SPA and DPA without distinguishing the encryption region. And by correlation-based electromagnetic analysis, measurement to disclosure of DES enhances 36 times with partial countermeasures and AES discloses no subkey after more than one million electromagnetic traces with full countermeasures.
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