Graphene has significant potential for application in electronics1-5, but cannot be used for effective field-effect transistors operating at room temperature because it is a semimetal with a zero bandgap6,7. Processing graphene sheets into nanoribbons with widths of less than 10nm can open up a bandgap that is large enough for room temperature transistor operation8-19, but nanoribbon devices often have low driving currents or transconductances18,19. Moreover, practical devices and circuits will require the production of dense arrays of ordered nanoribbons, which is of significant challenge20,21. Here we report the production of a new graphene nanostructure - which we call graphene nanomesh - that can open up a band gap in a large sheet of graphene to create a semiconducting thin film. The nanomeshes are prepared with block copolymer lithography and can have variable periodicities and neck widths down to 5 nm. Graphene nanomesh field-effect transistors can support currents nearly 100 times greater than individual graphene nanoribbon devices, and the on-off ratio - which is comparable with the values achieved in individual nanoribbon devices - can be tuned by varying the neck width. The block copolymer lithography approach used to make the nanomesh devices is intrinsically scalable and could allow for the rational design and fabrication of graphene-based devices and circuits with standard semiconductor processing.

Supercapacitors represent an important strategy for electrochemical energy storage, but are usually limited by relatively low energy density. Here we report a three-dimensional holey graphene framework with a hierarchical porous structure as a high-performance binder-free supercapacitor electrode. With large ion-accessible surface area, efficient electron and ion transport pathways as well as a high packing density, the holey graphene framework electrode can deliver a gravimetric capacitance of 298 F g À 1 and a volumetric capacitance of 212 F cm À 3 in organic electrolyte. Furthermore, we show that a fully packaged device stack can deliver gravimetric and volumetric energy densities of 35 Wh kg À 1 and 49 Wh l À 1 , respectively, approaching those of lead acid batteries. The achievement of such high energy density bridges the gap between traditional supercapacitors and batteries, and can open up exciting opportunities for mobile power supply in diverse applications.

Bernal stacked (AB stacked) bilayer graphene is of significant interest for functional electronic and photonic devices due to the feasibility to continuously tune its band gap with a vertical electrical field. Mechanical exfoliation can be used to produce AB stacked bilayer graphene flakes but typically with the sizes limited to a few micrometers. Chemical vapor deposition (CVD) has been recently explored for the synthesis of bilayer graphene but usually with limited coverage and a mixture of AB and randomly stacked structures. Herein we report a rational approach to produce large-area high quality AB stacked bilayer graphene. We show that the self-limiting effect of graphene growth on Cu foil can be broken by using a high H2/CH4 ratio in a low pressure CVD process to enable the continued growth of bilayer graphene. A high temperature and low pressure nucleation step is found to be critical for the formation of bilayer graphene nuclei with high AB stacking ratio. A rational design of a two-step CVD process is developed for the growth of bilayer graphene with high AB stacking ratio (up to 90 %) and high coverage (up to 99 %). The electrical transport studies demonstrated that devices made of the as-grown bilayer graphene exhibit typical characteristics of AB stacked bilayer graphene with the highest carrier mobility exceeding 4,000 cm2/V·s at room temperature, comparable to that of the exfoliated bilayer graphene.

Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H2O2) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H2O2) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and re-nucleate on the sidewalls of nanowires to initiate new etching pathways to produce porous structure. The elucidation of this fundamental formation mechanism opens a rational pathway to the production of wafer-scale single crystalline porous silicon nanowires with tunable surface areas ranging from 370 m2·g−1 to 30 m2·g−1, and can enable exciting opportunities in catalysis, energy harvesting, conversion, storage, as well as biomedical imaging and therapy.