With the advances of electronic information technology and computer network, especially the embedded technology, smart home is no more just a vision but being practical. The interoperability of heterogeneous devices and flexibility of devices' usage are two key problems that challenge the implementation of smart home. To deal with these two issues, this paper proposes an event-driven service oriented architecture using device profile for web services (DPWS). DPWS inherits the advantages of the traditional web services in achieving interoperability without dependence on platform, while improving service discovery and security as well as being optimized for deploying on resource constrained devices. By providing a visual interface for describing a service workflow (SW), the user can easily customize the actions of devices by services composition. Devices automatically cooperate without user's intervention to complete required business logic. This is achieved by fully exploiting the eventing capabilities on DPWS enabled home devices. Finally, a home theater scenario is given to illustrate the event driven mechanism for the SW in the proposed smart home framework.
The Graph Attention Networks (GATs) exhibit outstanding performance in multiple authoritative node classification benchmark tests (including transductive and inductive). The purpose of this research is to implement an FPGA-based accelerator called FPGAN for graph attention networks that achieves significant improvement on performance and energy efficiency without losing accuracy compared with PyTorch baseline. It eliminates the dependence on digital signal processors (DSPs) and large amounts of on-chip memory and can even work well on low-end FPGA devices. We design FPGAN with software and hardware co-optimization across the full stack from algorithm through architecture. Specifically, we compress model to reduce the model size, quantify features to perform fixed-point calculation, replace multiplication addition cell (MAC) with shift addition units (SAUs) to eliminate the dependence on DSPs, and design an efficient algorithm to approximate SoftMax function. We also adjust the activation functions and fuse operations to further reduce the computation requirement. Moreover, all data is vectorized and aligned for scalable vector computation and efficient memory access. All the above optimizations are integrated into a universal hardware pipeline for various structures of GATs. We evaluate our design on an Inspur F10A board with an Intel Arria 10 GX1150 and 16 GB DDR3 memory. Experimental results show that FPGAN can achieve 7.34 times speedup over Nvidia Tesla V100 and 593 times over Xeon CPU Gold 5115 while maintaining accuracy, and 48 times and 2400 times on energy efficiency respectively.
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