SiO2 is the most significantly used insulator layer in semiconductor devices. Its functionality was recently extended to resistance switching random access memory, where the defective SiO2 played an active role as the resistance switching (RS) layer. In this report, the bias-polarity-dependent RS behaviours in the top electrode W-sputtered SiO2-bottom electrode Pt (W/SiO2/Pt) structure were examined based on the current-voltage (I-V) sweep. When the memory cell was electroformed with a negative bias applied to the W electrode, the memory cell showed a typical electronic switching mechanism with a resistance ratio of ~100 and high reliability. For electroforming with opposite bias polarity, typical ionic-defect-mediated (conducting filament) RS was observed with lower reliability. Such distinctive RS mechanisms depending on the electroforming-bias polarity could be further confirmed using the light illumination study. Devices with similar electrode structures with a thin intervening Si layer between the SiO2 and Pt electrode, to improve the RS film morphology (root-mean-squared roughness of ~1.7 nm), were also fabricated. Their RS performances were almost identical to that of the single-layer SiO2 sample with very high roughness (root-mean-squared roughness of ~10 nm), suggesting that the reported RS behaviours were inherent to the material property.
TaO has been an appealing contender for the resistance switching random access memory (ReRAM). The resistance switching (RS) in this material is induced by the repeated formation and rupture of the conducting filaments (CFs) in the oxide layer, which are accompanied by the almost inevitable randomness of the switching parameters. In this work, a 1 to 2 nm-thick Ti layer was deposited on the 10 nm-thick TaO RS layer, which greatly improved the RS performances, including the much-improved switching uniformity. The Ti metal layer was naturally oxidized to TiO (x < 2) and played the role of a series resistor, whose resistance value was comparable to the on-state resistance of the TaO RS layer. The series resistor TiO efficiently suppressed the adverse effects of the voltage (or current) overshooting at the moment of switching by the appropriate voltage partake effect, which increased the controllability of the CF formation and rupture. The switching cycle endurance was increased by two orders of magnitude even during the severe current-voltage sweep tests compared with the samples without the thin TiO layer. The Ti deposition did not induce any significant overhead to the fabrication process, making the process highly promising for the mass production of a reliable ReRAM.
Reliability and uniformity in resistance switching behaviours in top electrode Cu-sputtered TiO2-bottom electrode Pt memory structure were greatly improved by inserting an interface layer of 5 nm-thick HfO2 between Cu and 50 nm-thick TiO2. The thin HfO2 layer, with much smaller cluster size than TiO2, limited the Cu migration appropriately and induced more uniform Cu conducting filament distribution. The repeated rejuvenation and rupture of Cu filament was limited within the HfO2 layer, thereby improving the switching reliability and uniformity. This also greatly decreased operation power compared to a memory cell without the thin HfO2 layer.
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