With the continued maturation of III–V nanowire research, expectations of material quality should be concomitantly raised. Ideally, III–V nanowires integrated on silicon should be entirely free of extended planar defects such as twins, stacking faults, or polytypism, position-controlled for convenient device processing, and gold-free for compatibility with standard complementary metal–oxide–semiconductor (CMOS) processing tools. Here we demonstrate large area vertical GaAsxSb1–x nanowire arrays grown on silicon (111) by molecular beam epitaxy. The nanowires’ complex faceting, pure zinc blende crystal structure, and composition are mapped using characterization techniques both at the nanoscale and in large-area ensembles. We prove unambiguously that these gold-free nanowires are entirely twin-free down to the first bilayer and reveal their three-dimensional composition evolution, paving the way for novel infrared devices integrated directly on the cost-effective Si platform.

Nanowire-based field-effect transistors are among the most promising means of overcoming the limits of today's planar silicon electronic devices, in part because of their suitability for gate-all-around architectures, which provide perfect electrostatic control and facilitate further reductions in "ultimate" transistor size while maintaining low leakage currents. However, an architecture combining a scalable and reproducible structure with good electrical performance has yet to be demonstrated. Here, we report a high performance field-effect transistor implemented on massively parallel dense vertical nanowire arrays with silicided source/drain contacts and scaled metallic gate length fabricated using a simple process. The proposed architecture offers several advantages including better immunity to short channel effects, reduction of device-to-device variability, and nanometer gate length patterning without the need for high-resolution lithography. These benefits are important in the large-scale manufacture of low-power transistors and memory devices.

Silicon nanostructure patterning with tight geometry control is an important challenge at the bottom level. In that context, stress based controlled oxidation appears to be an efficient tool for precise nanofabrication. Here, we investigate the stress-retarded oxidation phenomenon in various silicon nanostructures (nanobeams, nanorings and nanowires) at both the experimental and the theoretical levels. Different silicon nanostructures have been fabricated by a top-down approach. Complex dependence of the stress build-up on the nano-object's dimension, shape and size has been demonstrated experimentally and physically explained by modelling. For the oxidation of a two-dimensional nanostructure (nanobeam), relative independence to size effects has been observed. On the other hand, radial stress increase with geometry downscaling of a one-dimensional nanostructure (nanowire) has been carefully emphasized. The study of shape engineering by retarded oxidation effects for vertical silicon nanowires is finally discussed.

In-depth understanding of the retarded oxidation phenomenon observed during the oxidation of silicon nanostructures is proposed. The wet thermal oxidation of various silicon nanostructures such as nanobeams, concave/convex nanorings and nanowires exhibits an extremely different and complex behavior. Such effects have been investigated by the modeling of the mechanical stress generated during the oxidation process explaining the retarded regime. The model describes the oxidation kinetics of silicon nanowires down to a few nanometers while predicting reasonable and physical stress levels at the Si/SiO 2 interface by correctly taking into account the relaxation effects in silicon oxide through plastic flow. * christophe.krzeminski@isen.fr † guilhem.larrieu@laas.fr 1 Retarded oxidation where the oxide growth slows down very rapidly with oxidation duration or with the silicon nanoobject dimension is still a puzzling physical effect [1][2][3]. This physical effect can be viewed as a technological nanoscale tool able to control the nanoobjects shape, size distribution interface properties and could be used in many applications [4]. However, only very few studies have been dedicated to the understanding of the phenomenon which remains fragmented and limited [5][6][7]. In this work, oxidation kinetics have been investigated both on the experimental and theoretical counterparts in order to improve the understanding of the mechanisms of retarded mechanisms and to quantify the amount of stress generated at the Si/SiO 2 interface in silicon nanostructures.With the current top-down fabrication capabilities, etched silicon nanostructures including nanobeams, nanorings and nanowires have been fabricated with a high resolution [8] and then wet oxidized at 850• C. The seminal work of Kao et al. [9,10] with micrometer size of 2D cylindric object is revisited but in the nanometric range. Experimentally, the oxidation kinetics have been observed to be strongly dependent on the size and the geometry of the nanoobject. The oxide growth on Si nanobeams of previous width L is clearly thicker than a SiNWs with the diameter d = L. A size dependent oxidation kinetic was not observed in these structures whatever the nanobeam width considered. These experimental results illustrate 2 that the silicon oxidation retarded mechanism is strongly dependent at the nanoscale level on the nanoobject i) dimension ii) size and iii) shape.These dependences cannot be explained by the standard Deal and Grove oxidation model[11], as for example, a larger oxidant concentration for the smallest particles should in principle lead to a higher oxidation rate. Two main theories have been put forward to explain the retarded/self-limiting kinetics factor. The first one is the "stress limited reaction rate" assumption [6] with a radial stress build-up at the Si/SiO 2 interface assumed to be linearly dependent of the oxidation time up to a critical stress estimated to a few GPa where the oxidation rate would be completely negligible. The second theory is the ...

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The composition and band gap of the shell that formed during the growth of axial GaAs/GaAs 81 Sb 19 / GaAs heterostructure nanowires have been investigated by transmission electron microscopy combined with energy dispersion spectroscopy, scanning tunneling spectroscopy, and density functional theory calculations. On the GaAs 81 Sb 19 intermediate segment, the shell is found to be free of Sb (pure GaAs shell) and transparent to the tunneling electrons, despite the (110) biaxial strain that affects its band gap. As a result, a direct measurement of the core band gap allows the quantitative determination of the band offset between the GaAs 81 Sb 19 core and the GaAs shell and identifies it as a type I band alignment. V