We propose a specifically designed structure to fabricate thin-film transistors using amorphous indium-gallium-zinc-oxide (a-IGZO) films as the active channel layers. The I-shaped gate electrode is employed to define the channel width, reducing overlaps between the gate and source/drain electrodes. The devices with such a structure exhibit acceptable electrical performance and stability after annealing treatment. The XPS data show that the as-deposited a-IGZO film has not a very dense structure that may induce shallow traps. A shallow trap model is proposed to explain the large threshold voltage shifts of the as-deposited device. Annealing treatment can eliminate these shallow traps and improve the device stability.
The effects of post-annealing on performance of ZnO-based thin-film transistors (TFTs) fabricated at room temperature were investigated. It was observed that high-temperature annealing resulted in a large decrease in resistivity of the ZnO channel layer and caused a large off-state current for ZnO TFTs, while low-temperature annealing had little effect on the off-state current. The evolution of electrical performance of ZnO TFTs annealed at a lower temperature showed that the threshold voltage decreased greatly and the sub-threshold slope improved evidently without great change of the resistivity of the ZnO channel as the annealing time prolonged. The possible mechanism is that the traps have been removed without activating the donor defects in the ZnO channel layer.
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