SUMMARYThis paper distinguishes two kinds of algebra, namely switching algebra and binary signal algebra, in which switching and binary signal variables describe switching states of MOS transistors and signals in digital circuits respectively. Threshold comparison operations, transmission operation and union operation are introduced to connect these two algebras. These new operations conform to the action principle of MOS transistors. Based on the theory of transmission switches proposed in this paper, new design procedures for both constant and variable transmission sources are presented. The logic design of CMOS circuits at switch level is realized and CMOS circuits with simpler construction may be obtained by using variable transmission sources.
A novel power-efficient explicit-pulsed dual-edge triggered flip-flop (SEDNIFF) is proposed. The proposed SEDNIFF puts the latch node inside its structure, which not only simplifies the latch structure but also strengthens the robustness of the output signal. Based on the TSMC0.18 mm technology, the post-layout simulation results show that the proposed flip-flop gains an improvement of up to 17.9 and 23.5% in terms of total average power and power -delay product, respectively, as compared with its counterparts.Introduction: The clock system is one of the most power consuming components in a VLSI circuit, accounting for 30 -60% of the total power dissipation [1]. As flip-flops are the basic elements of the clock system, their choice and design has a profound effect both on reducing the power consumption and on providing more slack time for the time budget in high-performance systems. Thus, in order to achieve a high-performance system, the design of flip -flops is important.Pulse-triggered flip-flops are characterised by a simple structure, negative setup time and soft edge, performing better than traditional master-slave flip-flops [2]. Various kinds of pulse-triggered flip-flops were recently proposed [3 -6], including implicit-pulsed flip -flops and explicit-pulsed flip -flops. The pulse generator of the explicit-pulsed flip-flop can be shared by neighbouring homogeneous flip -flops, contributing to less power dissipation than implicit-pulsed ones [6]. Dual-edge flip-flops can reduce the clock frequency to half that of the single-edge flip-flop while maintaining the same data throughput, so power dissipation is decreased [7]. Thus, this Letter will mainly discuss explicit-pulsed dual-edge triggered flip-flops.A static output-controlled discharge flip-flop (SCDFF) is proposed in [4]. SCDFF uses cross-coupled inverters to keep the data at the output Q. However, the cross-coupled inverters have race problems, which not only degrade the speed of charging and discharging, but also cause short-circuit current power dissipation. If the output load capacitance is large, the duration of the race current will be prolonged, which increases the dynamic power consumption and may even distort the output signal.
Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.
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