In today's semiconductor industry downscaling of the IC design puts a stringent requirement on pattern overlay control. Tighter overlay requirements lead to exceedingly higher rework rates, meaning additional costs to manufacturing. Better alignment control became a target of engineering efforts to decrease rework rate for high-end technologies.Overlay performance is influenced by known parameters such as "Shift, Scaling, Rotation, etc", and unknown parameters defined as "Process Induced Variation", which are difficult to control by means of a process automation system. In reality, this process-induced variation leads to a strong wafer to wafer, or lot to lot variation, which are not easy to detect in the mass-production environment which uses sampling overlay measurements for only several wafers in a lot. An engineering task of finding and correcting a root cause for Process Induced Variations of overlay performance will be greatly simplified if the unknown parameters could be tracked for each wafer.This paper introduces an alignment performance monitoring method based on analysis of automatically generated "AWE" files for ASML scanner systems. Because "AWE" files include alignment results for each aligned wafer, it is possible to use them for monitoring, controlling and correcting the causes of "process induced" overlay performance without requiring extra measurement time. Since "AWE" files include alignment information for different alignment marks, it is also possible to select and optimize the best alignment recipe for each alignment strategy. Several case studies provided in our paper will demonstrate how AWE file analysis can be used to assist engineer in interpreting pattern alignment data.Since implementing our alignment data monitoring method, we were able to achieve significant improvement of alignment and overlay performance without additional overlay measurement time. We also noticed that the rework rate coming from alignment went down and stabilized at quite satisfactory level.
The downscaling of IC design rule has increasingly imposed tighter overlay tolerances together with high cost of lithography equipment. Foundries are required to optimize tools utilization in order to be cost effective. To run with the same process flow using different exposure tools, the effect of the different process parameters needs to be characterized. This paper explores the feasibility of using the same W-CMP process for two different alignment systems employing different alignment marks. An evaluation of the alignment performance was done using marks placed in the scribe line of Tower's products. Exposures were performed using two different DUV scanners at BEOL layers, with process splits performed prior to the W-CMP phase. Robustness of alignment mark is critical, as the scanner's alignment system requires accurate signal to precisely align a pattern layer to a pervious layer. Data taken by the scanners on various tool/mark/recipe combinations is analyzed to provide indication of the overlay performance robustness to the process parameters. To investigate the effect of different W-CMP processes on alignment marks in back-end processing, an evaluation was performed through which both mark design and process parameters were varied. The robustness of typical long-term process variation at the W-CMP step in a production environment was evaluated.
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