The optimization of high speed channel demands more challenging tasks such as estimating the noise from the interaction between signal nets and power nets, assessing the on-chip Power Delivery Network (PDN) effectiveness, and including the Power Delivery (PD) to signal coupling noise into the channel budget. However, even just identifying what to optimize in high-speed channel is difficult task, and obtaining meaningful parameters including interaction between signal integrity and power integrity is more challenging. The proposed analysis method employs accurate and more effective ways to find controllable parameters to optimize the channel response for the best performance in the high speed channel considering both signal integrity (SI) and power integrity (PI) interactions by utilizing response decomposition in the time domain with worst case pattern consideration.
Three-dimensional Integrated Circuits provide a solution to overcome bottlenecks in performance and power management issues. However, the drawback arises in the form of increased thermal density that results in thermal gradients that affect signal integrity. Since, the clock signal is critical for ensuring the performance of synchronous digital systems, its design is very important. In this paper we analyze the effect of thermal gradient on the clock distribution networks in the context of 3D ICs. We also propose novel methods for compensating the thermal effects which have been validated through extensive simulations and preliminary hardware measurements.
This paper discusses the link-level impact and design guidelines of stitching vias and stitching capacitors for highspeed differential systems. Consistent results were obtained between test board VNA/TDR characterization and 3D fullwave EM modeling. While the number and distance of stitching vias and decaps have little or no impact on differential mode crosstalk and ISI, their impact on commonmode crosstalk and ISI is high. Furthermore, effectiveness of stitching capacitors is relatively low at high frequencies comparing to stitching vias. Link-level time domain analysis was also performed to confirm the impact. Finally, a routing guideline for platform design was recommended for stitching vias and capacitors. IntroductionPlatform stitching vias and stitching capacitors have been proved to be critical design components for single-ended interface to facilitate return current path and minimize noise coupling from power plane to signal nets [1,2]. Fig. 1 shows modeling data that demonstrates the significant importance of stitching via for high speed single-ended buses. Tightened stitching distance rule is required for multi-GHz interfaces. As high-speed differential interfaces are adopted more often, a link-level impact assessment and design guidelines for plane stitching vias and decaps are highly desirable for SI engineers and platform designers. Looser stitching/decoupling requirement means spacious board routing, lower cost, and reduced design effort, but its exact indication on platform signal integrity design is unclear. The paper attempts to address this question. Previous studies have shown the impact of non-ideal return path on differential signaling either from an individual component perspective (e.g., [3]), or focusing on numerical analysis (e.g., [6,7]). EMI resulting from the signal via transition was also reported [4]. In addition, a few investigations have been done to analyze the power plane to signal nets noise coupling due to via transition (e.g., [2,5,8]). This paper will address the system level impact with decomposition of common mode and differential mode by utilizing a test vehicle.The study took a combinational approach of test board high frequency characterization (VNA/TDR) and computational 3D full-wave EM modeling. A dedicated test board was built for various stitching distances and via/cap number combinations. Both VNA and TDR measurements
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