No abstract

Abstract-Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBM's contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

No abstract

No abstract

The post-silicon validation phase in a processor's design life cycle is geared towards finding all remaining bugs in the system. It is, in fact, our last opportunity to find functional and electrical bugs in the design before shipping it to customers.In this paper, we provide a high-level overview of the methodology and technologies put into use as part of the POWER8 post-silicon functional validation phase. We describe the results and list the primary factors that contributed to this highly successful bring-up.

This paper targets to show feasibility of a three-dimensional process simulation flow in the context of optimization of the device design and the underlying fabrication processes. The simulation is based on and refers to the development of the SOI-based 30 nm FinFET devices. The major goal of the simulation work is to implement a complete FinFET process flow into a commercially available 3D process simulation environment. Furthermore, all important three-dimensional geometrical features, such as corner roundings and 3D facets, have been introduced into the simulation set-up. After the successful demonstration of a functional 3D process simulation flow, detailed issues of process simulation methodology are assessed, such as the usage of different dopant diffusion models or the modelling of specific oxidation processes plus assessment of different annealing conditions. Finally, a comparison of the simulation results with electrical measurement data is performed which shows fairly good agreement.

We present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 48nm node. The key technology enablers are a new cell architecture "Wordline over Bitline" (WOB)-realizing a high degree of self-alignment and small parasitic capacitances, together with high performance periphery C devices at reduced internal voltage, and the integration of a BS MIC/ HfSiO trench capacitor.

A high-end eServer consists of multiple microprocessor chips packaged with additional chips on a multichip module. In conjunction with memory and various I/O cards, this module is mounted on a card called a processor book, and a few of those cards on a board finally represent a major part of the system. Before the first hardware is built, simulations must be performed to verify that all of these components work together. But before we can build the simulation models, we need to find answers to many questions and to specify constraints, such as the scope of the simulation, the representation of the packaging data, the handling of cross-hierarchical connections such as cables, and the handling of passive components such as resistors and capacitors. This system model build should be as flexible as possible. System verification must be done for different system configurations (both single-processor and multiprocessor systems, one-processor-book systems, and multiprocessor-book systems) with or without I/O. Therefore, not only should a configurable model build downsize the model structure, but it should provide the capability to add logic. The requirement to include special logic, such as clock macros or checker logic, is driven by the use of emulation and acceleration technology and by other speed-related elements. This paper discusses these new concepts in eServer development: a configurable simulation model build, the automatic derivation of structural model data from packaging design, and the addition of specific logic without affecting the model structure generated by the previous step.