Improvement of traditional ASIC design methodology is targeted towards achieving signijkant increase in design productivity, This is especially critical in handling complex system-on-achip (SOC) products that allows only short design cycle. In order to meet delivery time and avoid loss of opportunity to market, a technique that allows reuse of pre-designed intellectual properties (IP ' s) must be developed.Designers at MIMOS' Microelectronics Lab focus on quick integration of CPU pzripherals and memoly blocks to a flexible system interconnect architecture ('A) to aggressively shorten design time. This paper describes a versatile approach in IA-based SOC design and gives a detail accounts of integration of a variety of IP 's to the IA.I.
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