In 1987, an analysis of the relationship between the conductor density of various substrates and their cost was made and a generalized plot showing these relationships was derived by the author. Since that time, a number of empirical studies and further theoretical derivations. using this plot as a basis, have been reported, notably by D. Kelemen, M. Clary and E. van Andel, in an effort to establish some general packaging rules or figures of merit which are useful for electronic design and packaging engineers. This paper will summarize the more recent studies and then will extend and apply some of the developed concepts for the derivation of new equations which can provide information about the most cost-efficient design to be used with a given or a selected This theoretical derivation indicates clearly that there exists a set of "saddle-shaped "CosVdensity relationships for each technology selected for the manufacture of the interconnecting substrates and which are influenced by the conductor density capability, material costs and the manufacturing yields. Practical application of these theoretically derived equations will be illustrated by empirical results confirming their applicability in aq realistic design environment.The paper will conclude with an example showing the application of the derived equations to the problem of packaging an CPU with 6*106 gates, using the most efficient interconnection solution for the entire system, including chips, MCMs and Motherboards. p 2 8 $0'
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