Medium to large physically-indexed low-associativity caches, where physical page number bits index the cache, present two problems.First, cache miss rate varies between runs, a.s data location in the cache depends on the placement of virtual pages in physical memory.Secondly, the virtual-to-physical address translation must precede cache indexing, increasing latency. This paper summarizes simulation results of instruction, data, and unified caches with conventional page allocation, and explores improving the mean miss rate by controlling (coloring) page allocation. A more strict page coloring algorithm reduces latency by allowing cache indexing to precede address translation.
Abstract-Address base-plus-offset summing is merged into the decode structure of this 64-KByte (512-Kbit), four-way setassociative cache. This address adder avoids time-consuming carry propagation by using an A + B = K A + B = K A + B = K equality test. The combined add and access operations are implemented using delayed-reset logic and a 0.25-m process. This wave pipelined RAM achieves a 1.6-ns cycle time and 2.6-ns latency for the combined address add and cache access.
Load latency contributes significantly to execution time. Because most cache accesses hit, cache-hit latency becomes an important component of expected load latency. Most modern microprocessors have base+offset addressing loads; thus effective cache-hit latency includes an addition as well as the RAM access.This paper introduces a new technique used in the UltraSPARC III microprocessor, Sum-Addressed Memory (SAM), which performs true addition using the decoder of the RAM array, with very low latency. We compare SAM with other methods for reducing the add part of load latency. These methods include sum-prediction with recovery, and bitwise indexing with duplicate-tolerance. The results demonstrate the superior performance of SAM.
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