<p>Machine Learning Operations (MLOps) streamline the lifecycle of machine-learning models in production. In recent years, the topic has picked the interest of practitioners, and consequently, a considerable number of tools and gray literature on architecting MLOps environments has emerged. However, this has created a new problem for organizations: selecting the most appropriate tools and design options for implementing their MLOps environments. To alleviate this problem, this paper proposes a reference architecture and requirements for MLOps by systematically reviewing 58 industrial gray literature articles. Such reference architecture drawn from the state of practice shall aid organizations in making better design and technology choices when embarking on their MLOps journey while providing a technology-independent baseline for further MLOps research. </p>
In continuation of a successful series of events, the 4th symposium of the Many-core Applications Research Community (MARC) took place at the Hasso Plattner Institute for Software Systems Engineering (HPI) in Potsdam. On December 8th and 9th 2011, researchers from different fields presented their current and future work on many-core hardware architectures, their programming models, and the resulting research questions for the upcoming generation of heterogeneous parallel systems.While the Intel Single Chip Cloud Computer (SCC) serves as common research platform for most MARC members, other interesting research on next generation many-core platforms was also discussed on this event. The symposium focused on topics such as• Operating system support for novel many-core architectures• Virtualization solutions to deal with hardware limitations• Dealing with legacy software on novel many-core architectures• New approaches for leveraging on-die messaging facilities • Traditional and new programming models for novel many-core hardware• Concepts for runtime systems on novel many-core hardware• Performance issues with modern on-die messaging facilities and caching infrastructures This proceedings include 14 papers from 5 symposium sessions. Every paper was reviewed by at least three reviewers from the program committee, consisting of:• Diana Göhringer (Fraunhofer IOSB)• Matthias Gries (Intel)• Werner Haas (Intel)• Prof. Dr. Hans-Ulrich Heiß (TU Berlin)• Jim P. Held (Intel)• Prof. Dr. Robert Hirschfeld HPI)• Ulrich Hoffmann (Intel)• Jason M. Howard (Intel)• Dr. Michael Hübner (Karlsruhe Institute of Technology)• Prof. Dr. Jörg Nolte (BTU Cottbus)• Prof. Dr. Andreas Polze (HPI)• Dr. Felix Salfner (SAP Innovation Center)• Prof. Dr. Bettina Schnor (Uni Potsdam)• Prof. Dr. Theo Ungerer (Universität Augsburg)• Dr. Peter Tröger (HPI)• Dr. Daniel Versick (University of Rostock)• Rob F. Van Der Wijngaart (Intel) We would like to thank our program committee members for their hard work and for their suggestions in the selection of papers. We would like to thank all those who submitted papers for their efforts and for the quality of their submissions. We also would like to thank Jan-Arne Sobania and Sabine Wagner for their assistance and support.Thank you for your active participation in the 4th MARC Symposium. We hope you found this event to be productive and enjoyable, and we look forward to seeing you next year at 5th MARC symposium and related events. Abstract-The Single-chip Cloud Computer (SCC), a 48 core experimental processor from Intel labs, is a platform for parallel programming research. Its hardware features and memory organization map naturally to message passing models. Standard and non-standard message passing libraries are already available for the SCC; one of the standard solutions is the RCKMPI library. RCKMPI's main features are three SCC specific MPICH2 channels. In this work, improvements to the SCCMPB channel are introduced; performance results for the new channel show better scaling with process count. The a...
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