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Performance of three kinds of bridge type fault current limiters (BTFCLs) for enhancing LVRT capability of DFIG is evaluated in this paper. The common BTFCL can effectively enhance the LVRT capability of DFIG. However, the fault current limiting inductor (FCLI) is periodically inserted into the stator circuit under normal operation for compensating power losses of the FCLI. The periodically insertion of the FCLI induces stator voltage spikes, which causes significant stator flux and electromagnetic torque oscillations. One feasible way to solve this problem is to use an additional current regulating circuit (CRC). However, the additional CRC increases hardware cost, reduces reliability of the whole system and induces more power losses. To solve this problem, a BTFCL with bypass resistor (BTFCL-BR) is presented. The bypass resistor absorbs the majority of the current harmonics during normal operation and eliminates the stator voltage spikes. The flux and electromagnetic torque oscillations can thus be significantly reduced. The performance of three kinds of BTFCLs is evaluated by simulation and experimental studies on a typical 1.5MW wind turbine driven DFIG system and a 2kW DFIG prototype. By simulation and experimental evaluations, it seems that the BTFCL-BR approach is the most promising solutions among the three kinds of BTFCLs.Index Terms-Doubly fed induction generator (DFIG), low voltage ride through (LVRT), bridge type fault current limiter (BTFCL).

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This study proposes control and design methods for a current source united power-quality conditioner (CS-UPQC). Unipolar modulation and parameter design methods are proposed for the series CS converter. The proposed modulation method doubles the equivalent switching frequency, which makes it possible to reduce the filter size and improve the control dynamics. Modified repetitive control schemes are presented for the voltage and current compensation strategies, which provide large open-loop control gains at the integral multiple of the fundamental frequency and guarantee good harmonics compensation performance. A fault current limiting scheme is also presented, which limits the fault current effectively by utilising the large DC link inductor of the CS-UPQC. Simulation results in Matlab/Simulink are presented to clarify the theory and feasibility of the proposed approaches.