A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory (NVM) is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 μm technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 μs over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of −193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about −115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than −52 dBc. The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.
This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18 m CMOS process. A low power mixed-signal LC VCO, a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time. The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations. The experimental results demonstrate that the power consumption of the synthesizer is about 4 mA @ 1.8 V and that the typical setting time of the synthesizer is less than 3 s.
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